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    Methods of forming electrical contacts
    11.
    发明授权
    Methods of forming electrical contacts 有权
    形成电触点的方法

    公开(公告)号：US08518812B2

    公开(公告)日：2013-08-27

    申请号：US13113281

    申请日：2011-05-23

    申请人： Marcello Mariani ,  Micaela Gabriella Tomasini

    发明人： Marcello Mariani ,  Micaela Gabriella Tomasini

    IPC分类号： H01L21/44

    CPC分类号： H01L29/401 ,  H01L21/743 ,  H01L27/1027 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/16

    摘要： Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches.

    摘要翻译： 一些实施方案包括形成接触的方法。 可以在半导体衬底上形成一排突起。 突起可以包括阵列的多个重复部件和端子突起。 端子突起可以具有通过电介质结构与衬底的半导体材料间隔开的牺牲材料。 可以沿着行形成导电线。 该线可以围绕端子突起的一端包围并分叉成两个沿着重复部件的相对侧的分支。 各个分支可以具有通过栅极电介质的段与牺牲材料隔开的区域。 牺牲材料可以与栅极电介质的段一起去除以形成接触开口。 可以在接触开口内形成导电接触，并直接抵靠分支的区域。

    Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
    12.
    发明授权
    Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling 有权
    制造具有改进的电容耦合的浮栅非易失性MOS半导体存储器件的方法

    公开(公告)号：US08384148B2

    公开(公告)日：2013-02-26

    申请号：US11317679

    申请日：2005-12-22

    申请人： Paolo Tessariol ,  Roberto Bez ,  Marcello Mariani

    发明人： Paolo Tessariol ,  Roberto Bez ,  Marcello Mariani

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.

    摘要翻译： 一种制造非易失性MOS半导体存储器件的方法包括在半导体材料衬底中形成由场氧化物填充的STI隔离区（浅沟槽隔离）和由所述STI隔离区彼此分离的存储单元的形成步骤。 存储单元包括通过第一介电层与所述半导体材料基板电隔离的栅电极，并且所述栅电极包括与所述STI隔离区自对准的浮置栅极。 该方法包括所述浮动栅极的形成阶段，其显示包括凹面的基本上鞍形; 所述浮栅的形成步骤包括第一共形导体材料层的沉积步骤。

    Methods of Forming Electrical Contacts
    13.
    发明申请
    Methods of Forming Electrical Contacts 有权
    形成电触点的方法

    公开(公告)号：US20120302052A1

    公开(公告)日：2012-11-29

    申请号：US13113281

    申请日：2011-05-23

    申请人： Marcello Mariani ,  Micaela Gabriella Tomasini

    发明人： Marcello Mariani ,  Micaela Gabriella Tomasini

    IPC分类号： H01L21/28 ,  H01L21/768

    CPC分类号： H01L29/401 ,  H01L21/743 ,  H01L27/1027 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/16

    摘要： Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches.

    摘要翻译： 一些实施方案包括形成接触的方法。 可以在半导体衬底上形成一排突起。 突起可以包括阵列的多个重复部件和端子突起。 端子突起可以具有通过电介质结构与衬底的半导体材料间隔开的牺牲材料。 可以沿着行形成导电线。 该线可以围绕端子突起的一端包围并分叉成两个沿着重复部件的相对侧的分支。 各个分支可以具有通过栅极电介质的段与牺牲材料隔开的区域。 牺牲材料可以与栅极电介质的段一起去除以形成接触开口。 可以在接触开口内形成导电接触，并直接抵靠分支的区域。

    SHALLOW TRENCH ISOLATION FOR A MEMORY
    14.
    发明申请
    SHALLOW TRENCH ISOLATION FOR A MEMORY 有权
    用于记忆的浅层分离

    公开(公告)号：US20120080738A1

    公开(公告)日：2012-04-05

    申请号：US13315337

    申请日：2011-12-09

    申请人： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    发明人： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    IPC分类号： H01L29/788

    CPC分类号： H01L29/788 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    摘要： In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

    摘要翻译： 在一些实施例中，具有在其侧面上的间隔物的栅极结构可以用作掩模以在诸如闪存的微电子存储器中形成自对准沟槽。 在一些实施例中，门结构的第一部分可以与侧壁间隔件一起用于形成掩模。 然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

    Process for the formation of dielectric isolation structures in semiconductor devices
    16.
    发明申请
    Process for the formation of dielectric isolation structures in semiconductor devices 审中-公开
    在半导体器件中形成绝缘隔离结构的工艺

    公开(公告)号：US20050009294A1

    公开(公告)日：2005-01-13

    申请号：US10853565

    申请日：2004-05-25

    申请人： Donata Piccolo ,  Lorena Beghin ,  Marcello Mariani ,  Chiara Savardi

    发明人： Donata Piccolo ,  Lorena Beghin ,  Marcello Mariani ,  Chiara Savardi

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/76232

    摘要： A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material.

    摘要翻译： 在硅衬底上形成电介质隔离结构的工艺包括在衬底中形成至少一个沟槽，在氧化环境中进行高温处理，以在沟槽的壁和底部形成二氧化硅的第一衬里层 ，并且进行二氧化硅沉积处理以在第一衬里层上形成第二衬里层。 还进行氮化硅沉积处理以在第二衬里层上形成第三衬里层。 沟槽填充有隔离材料。

    Method for manufacturing non volatile memory cells integrated on a semiconductor substrate
    20.
    发明申请
    Method for manufacturing non volatile memory cells integrated on a semiconductor substrate 审中-公开
    用于制造集成在半导体衬底上的非易失性存储单元的方法

    公开(公告)号：US20070202647A1

    公开(公告)日：2007-08-30

    申请号：US11647504

    申请日：2006-12-27

    申请人： Marcello Mariani ,  Emilio Camerlenghi ,  Emanuele Concari

    发明人： Marcello Mariani ,  Emilio Camerlenghi ,  Emanuele Concari

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/40114

    摘要： Non volatile memory cells are integrated on a semiconductor substrate, each cell comprising a floating gate electrode. These cells are made by depositing at least one protective layer on the semiconductor substrate, forming a first plurality of openings in the protective layer, etching the semiconductor substrate through the first plurality of openings so as to form a plurality of trenches, filling in the plurality of trenches and the first plurality of openings with an insulation layer, etching surface portions of the protective layer to form: surface portions of the insulation layer projecting from the semiconductor substrate divided from each other by a second plurality of openings, and lower portions of the protection layer confined below the second plurality of openings, etching the insulation layer to reduce the cross dimensions of the surface portions of the insulation layer, removing the lower portions of said protection layer until the semiconductor substrate is exposed.

    摘要翻译： 非易失性存储器单元集成在半导体衬底上，每个单元包括浮置栅电极。 这些电池通过在半导体衬底上沉积至少一个保护层而形成，在保护层中形成第一多个开口，通过第一多个开口蚀刻半导体衬底，以形成多个沟槽，填充多个 的沟槽和具有绝缘层的第一多个开口，蚀刻保护层的表面部分以形成：通过第二多个开口彼此分隔的从半导体衬底突出的绝缘层的表面部分，以及 保护层限制在第二多个开口下方，蚀刻绝缘层以减小绝缘层的表面部分的横截面尺寸，去除所述保护层的下部直到半导体衬底露出。