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    WAFER FOR FORMING IMAGING ELEMENT, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND IMAGING ELEMENT CHIP
    11.
    发明申请
    WAFER FOR FORMING IMAGING ELEMENT, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND IMAGING ELEMENT CHIP 有权
    用于形成成像元件的波形，制造固态成像元件的方法和成像元件芯片

    公开(公告)号：US20150048352A1

    公开(公告)日：2015-02-19

    申请号：US14496910

    申请日：2014-09-25

    Applicant: FUJIFILM CORPORATION

    Inventor： Takahiko ICHIKI

    IPC: H01L27/30 ,  H01L51/00 ,  H01L51/44

    CPC classification number: H01L27/307 ,  G01R31/2831 ,  G01R31/2884 ,  H01L27/14603 ,  H01L51/0031 ,  H01L51/441 ,  H01L51/448

    Abstract: A wafer for forming an imaging element has a test pattern and a plurality of imaging element units. The wafer has an imaging region which includes a great number of photoelectric conversion pixels, an imaging element units and a test pattern. The test pattern includes a testing organic photoelectric conversion film and a testing counter electrode having the same configuration and formed at the same time as the organic photoelectric conversion film and a counter electrode, respectively of the photoelectric conversion pixels. A first testing terminal is electrically connected to the undersurface side of the testing organic photoelectric conversion film, and a second testing terminal is electrically connected to the testing counter electrode. A protective film is formed over the entire semiconductor wafer so as to cover the imaging region and the test pattern, and is then partially removed so that a part of each testing terminal is exposed.

    Abstract translation: 用于形成成像元件的晶片具有测试图案和多个成像元件单元。 晶片具有包括大量光电转换像素，成像元件单元和测试图案的成像区域。 测试图案包括测试有机光电转换膜和具有相同配置的测试对电极，并且分别与有机光电转换膜和对电极分别形成在光电转换像素上。 第一测试端子电连接到测试有机光电转换膜的下表面侧，第二测试端子电连接到测试对电极。 在整个半导体晶片上形成保护膜以覆盖成像区域和测试图案，然后被部分地去除，使得每个测试端子的一部分被暴露。

    METHOD OF MANUFACTURING CONDUCTIVE FILM AND CONDUCTIVE FILM
    13.
    发明申请
    METHOD OF MANUFACTURING CONDUCTIVE FILM AND CONDUCTIVE FILM 审中-公开

    公开(公告)号：US20190333656A1

    公开(公告)日：2019-10-31

    申请号：US16460462

    申请日：2019-07-02

    Applicant: FUJIFILM Corporation

    Inventor： Takahiko ICHIKI

    IPC: H01B5/14 ,  H01B13/00 ,  G06F3/044 ,  C25D3/12 ,  C25D3/38 ,  C25D5/02 ,  C25D5/12 ,  C25D5/56

    Abstract: A method of manufacturing a conductive film includes forming a first metallic film containing nickel as a main component on at least one main surface of the transparent resin substrate so as to be in contact with the transparent resin substrate, forming a second metallic film containing copper as a main component on the first metallic film, forming, on the second metallic film, a resist film provided with openings in a region where the metallic thin wires are formed, removing the second metallic film in the openings, forming a third metallic film on the first metallic film in the openings by a plating method, removing the resist film, removing the second metallic film on the first metallic film, and removing the first metallic film using the third metallic film as a mask.

    TRANSISTOR AND MANUFACTURING METHOD OF TRANSISTOR
    15.
    发明申请
    TRANSISTOR AND MANUFACTURING METHOD OF TRANSISTOR 审中-公开

    公开(公告)号：US20170179413A1

    公开(公告)日：2017-06-22

    申请号：US15454247

    申请日：2017-03-09

    Applicant: FUJIFILM CORPORATION

    Inventor： Yoshihisa USAMI ,  Yoshiki MAEHARA ,  Takahiko ICHIKI

    IPC: H01L51/05 ,  H01L51/10

    CPC classification number: H01L51/0529 ,  H01L21/283 ,  H01L29/417 ,  H01L29/423 ,  H01L29/42384 ,  H01L29/49 ,  H01L29/4908 ,  H01L29/7869 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/105

    Abstract: A transistor and a manufacturing method of a transistor which prevents a decrease in mobility, prevents a decrease in a withstand voltage of the insulating layer, and prevents a short circuit between a gate electrode and a semiconductor layer due to curvature. A substrate having insulating properties, a source electrode and a drain electrode disposed in a surface direction of a main surface of the substrate by being separated from each other, a gate electrode disposed between the source electrode and the drain electrode in the surface direction of the substrate, a semiconductor layer disposed in contact with the source electrode and the drain electrode, and an insulating film disposed between the gate electrode and the semiconductor layer in a direction perpendicular to the main surface of the substrate are included, and a gap region is formed between the semiconductor layer and the insulating film.

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