公开(公告)号：US20150076622A1

公开(公告)日：2015-03-19

申请号：US14030506

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract translation: 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US10312150B1

公开(公告)日：2019-06-04

申请号：US15919594

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu ,  Joseph Kassim ,  Bharat Krishnan

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/475 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

公开(公告)号：US09640423B2

公开(公告)日：2017-05-02

申请号：US14813254

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bharat Krishnan ,  Shishir Ray ,  Jinping Liu

IPC: H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/763 ,  H01L21/02164 ,  H01L21/02345 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76882 ,  H01L21/76883 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

公开(公告)号：US09472465B2

公开(公告)日：2016-10-18

申请号：US14270824

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/32133 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66477

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，提供了一种用于制造集成电路的方法。 该方法包括在半导体衬底上的层间电介质材料的第二FET区域中的第一FET区域和第二FET沟槽中形成第一FET沟槽，至少部分地用功函数金属填充第一和第二FET沟槽以形成 功函数金属层，并且至少部分去除第二FET沟槽中的功函数金属层的一部分。 第一FET沟槽被定义为NFET沟槽，并且第二FET沟槽被定义为PFET沟槽。

公开(公告)号：US20150325681A1

公开(公告)日：2015-11-12

申请号：US14270824

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/32133 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66477

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，提供了一种用于制造集成电路的方法。 该方法包括在半导体衬底上的层间电介质材料的第二FET区域中的第一FET区域和第二FET沟槽中形成第一FET沟槽，至少部分地用功函数金属填充第一和第二FET沟槽以形成 功函数金属层，并且至少部分去除第二FET沟槽中的功函数金属层的一部分。 第一FET沟槽被定义为NFET沟槽，并且第二FET沟槽被定义为PFET沟槽。

公开(公告)号：US20150294915A1

公开(公告)日：2015-10-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。