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    DEVICE LAYOUT FOR REDUCING THROUGH-SILICON-VIA STRESS
    11.
    发明申请
    DEVICE LAYOUT FOR REDUCING THROUGH-SILICON-VIA STRESS 审中-公开
    用于减少通过硅 - 应力的器件布局

    公开(公告)号：US20150028482A1

    公开(公告)日：2015-01-29

    申请号：US13948442

    申请日：2013-07-23

    Applicant: Globalfoundries Inc.

    Inventor： Guoxiang Ning ,  Ming Lei ,  Paul Ackmann

    IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Approaches for reducing through-silicon via (TSV) stress are provided. Specifically, provided is a device comprising a substrate and a TSV formed in the substrate, the TSV having an element patterned therein. The TSV further comprises a set of openings adjacent the element that are subsequently filled with a TSV fill material. The element may be patterned according to any number of shapes (e.g., circle, oval, rectangle, etc.) to optimize the stress distribution for the TSV. The element is patterned and provided within the TSV in order to reduce or compensate for stress forces caused by a change in volume of the conductive fill materials of the openings of the TSV. These approaches apply to both single TSVs and a plurality of TSVs (e.g., arranged as a matrix).

    Abstract translation: 提供了减少硅通孔（TSV）应力的方法。 具体地，提供了包括在基板中形成的基板和TSV的器件，TSV具有图案化的元件。 TSV还包括邻近该元件的一组开口，随后填充有TSV填充材料。 元件可以根据任何数量的形状（例如，圆形，椭圆形，矩形等）进行图案化，以优化TSV的应力分布。 元件被图案化并提供在TSV内，以便减少或补偿由TSV的开口的导电填充材料的体积变化引起的应力。 这些方法适用于单个TSV和多个TSV（例如，排列为矩阵）。

    Circuit structures and methods of fabrication with enhanced contact via electrical connection
    12.
    发明授权
    Circuit structures and methods of fabrication with enhanced contact via electrical connection 有权
    电路结构和通过电气连接增强接触的制造方法

    公开(公告)号：US08907496B1

    公开(公告)日：2014-12-09

    申请号：US13909301

    申请日：2013-06-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： GuoXiang Ning ,  Xiang Hu ,  Sarasvathi Thangaraju ,  Paul Ackmann

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.

    Abstract translation: 电路结构和制造方法在例如第一金属水平和导电结​​构的接触表面之间提供增强的电连接。 使用多个不同尺寸的接触通孔实现增强的电连接，并且设置在接触表面上并电耦合到接触表面。 不同尺寸的接触通孔包括设置在接触表面的中心区域上的至少一个中心区域接触孔，以及设置在接触表面的周边区域上的至少一个周边区域接触孔，其中该至少一个中心区域接触 通孔大于至少一个周边区域接触通孔。

    RETICLE, SYSTEM COMPRISING A PLURALITY OF RETICLES AND METHOD FOR THE FORMATION THEREOF
    15.
    发明申请
    RETICLE, SYSTEM COMPRISING A PLURALITY OF RETICLES AND METHOD FOR THE FORMATION THEREOF 有权
    包含多种反应物的系统的制度及其形成方法

    公开(公告)号：US20160291457A1

    公开(公告)日：2016-10-06

    申请号：US14674157

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

    IPC: G03F1/36 ,  H01L21/768 ,  G03F7/30

    CPC classification number: G03F1/36

    Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

    Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

    OPTICAL PROXIMITY CORRECTION FOR CONNECTING VIA BETWEEN LAYERS OF A DEVICE
    17.
    发明申请
    OPTICAL PROXIMITY CORRECTION FOR CONNECTING VIA BETWEEN LAYERS OF A DEVICE 审中-公开
    用于通过设备层连接的光学近似校正

    公开(公告)号：US20150006138A1

    公开(公告)日：2015-01-01

    申请号：US13932141

    申请日：2013-07-01

    Applicant: Globalfoundries Inc.

    Inventor： Guo Xiang Ning ,  Fang Hong Gn ,  Paul Ackmann ,  Chin Teong Lim

    IPC: G06F17/50

    CPC classification number: G03F7/70441 ,  G03F1/36

    Abstract: Approaches for simulating a photolithographic process are provided. Specifically, provided is an optical proximity correction (OPC) model that includes kernel parameters corresponding to inter-layer activity and an etch process for a connecting via of an integrated circuit (IC). A resultant intensity is determined for a corresponding plurality of process variations corresponding to the interlayer activity and the etch process. As such, the OPC model considers both interlay activity and etch process.

    Abstract translation: 提供了用于模拟光刻工艺的方法。 具体地，提供了包括对应于层间活动的核参数和用于集成电路（IC）的连接通路的蚀刻处理的光学邻近校正（OPC）模型。 对于与层间活性和蚀刻工艺相对应的相应多个工艺变化确定合成强度。 因此，OPC模型考虑了interlay活动和蚀刻过程。

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