公开(公告)号：US09525027B2

公开(公告)日：2016-12-20

申请号：US14208518

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L21/225 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/1008 ,  H01L21/2254 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/4232 ,  H01L29/6625 ,  H01L29/66795 ,  H01L29/735 ,  H01L29/785

Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.

Abstract translation: 使用绝缘体上半导体衬底制造横向双极结晶体管。 晶体管包括在掺杂硅基区内的锗梯度，晶体管的集电极区域的方向上锗含量增加。 使用包括平行硅散热片的衬底来制造横向双极结晶体管有助于将CMOS FinFET器件和具有分级硅锗基极区域的横向双极结型晶体管包括在同一芯片上。

公开(公告)号：US20160268123A1

公开(公告)日：2016-09-15

申请号：US14645449

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/207 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L29/16 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/36

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Abstract translation: 一种在多孔半导体结构上形成半导体的方法。 该方法可以包括形成堆叠，堆叠包括（从底部到顶部）衬底，基底硅层，厚硅层和薄硅层，其中薄硅层和厚硅层被松弛; 使用多孔化方法将厚硅层转化为多孔硅层; 在薄硅层上形成III-V层，III-V层被松弛，薄硅层变形，多孔硅层部分变形。

公开(公告)号：US10199220B2

公开(公告)日：2019-02-05

申请号：US15652413

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US20180190797A1

公开(公告)日：2018-07-05

申请号：US15911415

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L21/324 ,  H01L21/321 ,  H01L21/768

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09793113B2

公开(公告)日：2017-10-17

申请号：US15075668

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/20 ,  H01L29/78 ,  H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/0243 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66446 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09601624B2

公开(公告)日：2017-03-21

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/167 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

公开(公告)号：US09514995B1

公开(公告)日：2016-12-06

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US09368492B2

公开(公告)日：2016-06-14

申请号：US14054009

申请日：2013-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/82 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02123 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7856

Abstract: A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.

Abstract translation: 半导体衬底可以通过提供一种提供绝缘体上半导体（SOI）衬底而形成，该衬底包括基底半导体层，在该半导体基底上方的掩埋绝缘体层，以及包含掩埋绝缘体层之上的第一半导体材料的SOI层 ; 在所述SOI层中形成隔离区，其将所述SOI层的第一部分与所述SOI层的第二部分隔离; 去除所述SOI层的所述第二部分以暴露所述掩埋绝缘体层的一部分; 在所述掩埋绝缘体层的暴露部分中形成孔以暴露所述基底半导体层的一部分; 以及在所述基底半导体层的所述暴露部分上形成由第二半导体材料制成的半导体层，使得所述替换半导体层覆盖所述掩埋绝缘体层的所述暴露区域。

公开(公告)号：US09305883B2

公开(公告)日：2016-04-05

申请号：US14620233

申请日：2015-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian Naczas ,  Vamsi Paruchuri ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

公开(公告)号：US09236397B2

公开(公告)日：2016-01-12

申请号：US14172365

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Jinghong Li ,  Sanjay Mehta ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L27/1211 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A composite spacer structure is formed on vertical sidewalls of a gate structure that is formed straddling a semiconductor fin. In one embodiment, the composite spacer structure includes an inner low-k dielectric material portion and an outer nitride material portion.

Abstract translation: 在跨越半导体鳍片的栅极结构的垂直侧壁上形成复合间隔物结构。 在一个实施例中，复合间隔物结构包括内部低k电介质材料部分和外部氮化物材料部分。