公开(公告)号：US08815685B2

公开(公告)日：2014-08-26

申请号：US13755246

申请日：2013-01-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicholas LiCausi ,  Jody Fronheiser ,  Errol Todd Ryan

IPC: H01L21/336 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3105 ,  H01L29/66795

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof. An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的方法。 根据一个实施例，该方法包括形成至少部分地由限制隔离材料界定的半导体衬底的一部分。 衬垫电介质覆盖在限制隔离材料上，并被处理以钝化其表面。 然后将半导体材料的外延层生长在半导体衬底的一部分上。

公开(公告)号：US10580696B1

公开(公告)日：2020-03-03

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/288

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US20190221473A1

公开(公告)日：2019-07-18

申请号：US16364465

申请日：2019-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76813 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US10181421B1

公开(公告)日：2019-01-15

申请号：US15647977

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan ,  Sean Xuan Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.

公开(公告)号：US20190013236A1

公开(公告)日：2019-01-10

申请号：US15643742

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to fully aligned via structures having relaxed gapfills and methods of manufacture. The method includes: selectively depositing a capping material on a conductive material within a plurality of interconnect structures to form capped interconnect structures; depositing at least one insulator material over the capped interconnect structures; forming a fully aligned via structure through the at least one insulator material to expose the capping material; filling the fully aligned via structure with an alternative metal; and depositing a metal material on the alternative metal in the fully aligned via structure.

公开(公告)号：US20170125288A1

公开(公告)日：2017-05-04

申请号：US15407872

申请日：2017-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a first dielectric material and a plurality of conductive lines disposed in the first dielectric material. Each of the plurality of conductive lines includes a conductive fill material and a liner layer disposed between at least a bottom surface of the conductive fill material and the first dielectric material. The first dielectric material defines at least one air gap between two of the plurality of conductive lines. The at least one air gap has a first depth greater than a second depth of the plurality of conductive lines.

公开(公告)号：US09466530B2

公开(公告)日：2016-10-11

申请号：US14526729

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在至少一层绝缘材料中形成开口，从而暴露至少一部分导电接触，进行选择性金属硅化物形成工艺以选择性地形成金属硅化物层 在所述开口中和在所述导电接触件上，在所述选择性形成的金属硅化物层上方沉积至少一种导电材料，以便过度填充所述开口，并进行至少一个平坦化处理，以便去除多余的材料，从而限定导电通孔 其位于开口中并且导电地耦合到选择性形成的金属硅化物层和导电接触。

公开(公告)号：US20160020140A1

公开(公告)日：2016-01-21

申请号：US14334385

申请日：2014-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed.

Abstract translation: 在一个实例中，一种方法包括在电介质材料上方或介质材料中形成掩模层。 电介质材料在包含碳吸气剂的环境气氛中暴露于光子辐射，以产生电介质材料的损坏部分。 掩模层阻挡光子辐射。 去除电介质材料的损坏部分。

公开(公告)号：US20150348833A1

公开(公告)日：2015-12-03

申请号：US14807480

申请日：2015-07-23

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Anh Duong ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L21/76843 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract translation: 可以选择性地对Ta / TaN阻挡衬垫和SiC硬掩模层进行蚀刻，例如，以减少潜在的铜污染。 铜膜可以比衬垫更凹入，以进一步增强保护。 可以使用包含HF和HCl的混合物的湿式蚀刻溶液来相对于衬垫材料选择性地蚀刻铜，例如，铜膜可以凹陷在2和3nm之间，并且阻挡衬里膜可以凹陷在1.5和 2 nm。

公开(公告)号：US20150340274A1

公开(公告)日：2015-11-26

申请号：US14286029

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Sukwon Hong

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02348 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823431 ,  H01L29/66795

Abstract: Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is formed within a trench. The insulating layer is infused with water, and the insulating layer is annealed while being irradiated. The insulating layer is annealed at a dry anneal temperature of about 800 degrees centigrade or less.

Abstract translation: 提供了集成电路的制造方法。 一种用于制造集成电路的方法包括形成覆盖在衬底上的绝缘层，其中绝缘层形成在沟槽内。 绝缘层注入水，绝缘层在照射下退火。 绝缘层在约800摄氏度或更低的干燥退火温度下退火。