公开(公告)号：US09331229B2

公开(公告)日：2016-05-03

申请号：US14147939

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L31/00 ,  H01L21/00 ,  H01L31/075 ,  H01L31/0304 ,  H01L31/074

CPC classification number: H01L31/075 ,  H01L31/03046 ,  H01L31/074 ,  Y02E10/544 ,  Y02P70/521

Abstract: An InxGa1-xAs interlayer is provided between a III-V base and an intrinsic amorphous semiconductor layer of a heterojunction III-V solar cell structure. Improved surface passivation and open circuit voltage may be obtained through the incorporation of the interlayer within the structure.

Abstract translation: 在III-V基极和异质结III-V族太阳能电池结构的本征非晶半导体层之间提供In x Ga 1-x As夹层。 可以通过在结构内并入中间层来获得改进的表面钝化和开路电压。

公开(公告)号：US09240432B2

公开(公告)日：2016-01-19

申请号：US14020473

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/146

CPC classification number: H01L27/14692 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.

公开(公告)号：US09478658B2

公开(公告)日：2016-10-25

申请号：US14717551

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L29/7841 ,  H01L29/785

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

公开(公告)号：US09356019B2

公开(公告)日：2016-05-31

申请号：US14700147

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber ,  Ghavam G. Shahidi

IPC: H01L29/868 ,  H01L27/06 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L27/0629 ,  H01L29/0847 ,  H01L29/8611 ,  H01L29/868

Abstract: An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

公开(公告)号：US09240355B2

公开(公告)日：2016-01-19

申请号：US14705397

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/861

Abstract: An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions.

Abstract translation: 一种电气装置，包括存在于SOI衬底的第一半导体器件区域中的第一导电半导体器件和存在于SOI衬底的第二半导体器件区域中的第二导电半导体器件。 电子器件还包括存在于SOI衬底的二极管区域内的二极管，其包括存在于SOI衬底的SOI层上的第一导电半导体材料的第一掺杂层。 第一掺杂层包括从第一连接基部延伸的第一多个突起。 半导体二极管还包括存在于第一掺杂层上的第二导电半导体材料的第二掺杂层。 第二掺杂层包括从第二连接基部延伸的第二多个突起。 第二多个突起存在于并分离第一多个突起之间。

公开(公告)号：US09425080B2

公开(公告)日：2016-08-23

申请号：US14600229

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Robert H. Dennard ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi

IPC: H01L21/762 ,  H01L27/115 ,  B82Y10/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/76251 ,  B82Y10/00 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11536 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

公开(公告)号：US09368420B2

公开(公告)日：2016-06-14

申请号：US14732689

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Wilfried E. Haensch ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/01 ,  H01L23/14 ,  H01L27/12 ,  H01L27/092 ,  H01L23/538 ,  H01L21/762

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L21/7624 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/5387 ,  H01L27/092 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

公开(公告)号：US09224755B2

公开(公告)日：2015-12-29

申请号：US14020098

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/3262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/1266 ,  H01L27/3248 ,  H01L51/5218 ,  H01L51/5221 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract translation: 使用适用于柔性基板的技术制造高分辨率有源矩阵结构。 包括有源半导体器件的背板层使用绝缘体上半导体衬底形成。 使用层转移技术或化学/机械加工使衬底变薄。 在衬底的半导体层上形成驱动晶体管以及提供计算或感测等其它功能的附加电路。 与诸如有机发光二极管的无源器件的接触可以由形成在衬底的手柄层中的重掺杂区域提供，然后被隔离。 可以在用作沟道层的半导体层上形成栅极电介质层，或者可以将衬底的绝缘体层用作栅极介电层。