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    Semiconductor gate structure for threshold voltage modulation and method of making same
    11.
    发明授权
    Semiconductor gate structure for threshold voltage modulation and method of making same 有权
    用于阈值电压调制的半导体栅极结构及其制造方法

    公开(公告)号：US08932923B2

    公开(公告)日：2015-01-13

    申请号：US13770493

    申请日：2013-02-19

    Applicant: Globalfoundries, Inc.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L21/8238 ,  H01L29/40 ,  H01L29/49

    CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

    Abstract translation: 具有NFET和PFET的半导体器件的栅极结构包括在NFET和PFET的栅极上方的基于铪的电介质的下层和镧系元素电介质的上层。 将电介质退火以将其混合在NFET上方，导致降低的功函数和相应的阈值电压降低。 在NFET栅极上方的混合电介质上的退火的较厚的氮化钛盖也降低了功函数和阈值电压。 在PFET栅极上的TiN盖和铪基电介质之上，是未经退火的另一层氮化钛。 钨的导电层覆盖该结构。

    METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES
    12.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES 有权
    基于CMOS的集成电路产品和结果设备的门结构形成方法

    公开(公告)号：US20140367790A1

    公开(公告)日：2014-12-18

    申请号：US13919676

    申请日：2013-06-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kisik Choi ,  Ruilong Xie

    IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/28

    CPC classification number: H01L21/823443 ,  H01L21/28008 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66545

    Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.

    Abstract translation: 本文公开的一种说明性方法包括通过从相同的材料形成栅极绝缘层和用于器件的第一金属层并且仅在第一金属层上选择性地形成金属硅化物材料层来形成用于NMOS晶体管和PMOS晶体管的替代栅极结构 对于NMOS器件，但不在PMOS器件上。 本文公开的新颖的集成电路产品的一个示例包括NMOS器件和PMOS器件，其中栅极绝缘层和器件的栅极结构的第一金属层由相同的材料制成，NMOS器件的栅极结构包括 位于所述NMOS器件的所述第一金属层上的金属硅化物材料，以及位于所述NMOS器件的所述金属硅化物材料上以及所述PMOS器件的所述第一金属层上的第二金属层。

    METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES
    13.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES 有权
    基于CMOS的集成电路产品和结果设备的门结构形成方法

    公开(公告)号：US20140367788A1

    公开(公告)日：2014-12-18

    申请号：US13918569

    申请日：2013-06-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Kisik Choi

    IPC: H01L21/8234 ,  H01L27/092

    CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/42356 ,  H01L29/4975

    Abstract: One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.

    Abstract translation: 本文公开的一种说明性方法包括从相同材料形成用于NMOS和PMOS器件的栅极绝缘层和第一金属层，仅选择性地形成用于PMOS器件的第一金属层，以及在NMOS和PMOS栅极内形成不同形状的金属硅化物区域 空腔 本文公开的新型集成电路产品包括具有NMOS栅极绝缘层的NMOS晶体管，具有大致矩形横截面构造的NMOS金属硅化物和位于NMOS金属硅化物区域上的NMOS金属层。 该产品还包括具有相同栅极绝缘材料的PMOS晶体管，第一PMOS金属和PMOS金属硅化物区域，其中NMOS和PMOS金属硅化物区域由相同的金属硅化物组成。

    Methods of forming gate structures for transistor devices for CMOS applications
    20.
    发明授权
    Methods of forming gate structures for transistor devices for CMOS applications 有权
    为CMOS应用形成晶体管器件的栅极结构的方法

    公开(公告)号：US09105497B2

    公开(公告)日：2015-08-11

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

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