公开(公告)号：US09029214B2

公开(公告)日：2015-05-12

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ran Yan

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。

公开(公告)号：US20150021703A1

公开(公告)日：2015-01-22

申请号：US13943229

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/78

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract translation: 在各个方面，提供了形成半导体器件和半导体器件的方法。 在本文的一些说明性实施例中，硅/锗层设置在半导体衬底上。 在硅/锗层上形成至少一个绝缘材料层。 在进行热退火处理之后，在随后的处理顺序中除去至少一个绝缘材料层，使得硅/锗层至少部分暴露。 在随后施加的另外的处理顺序中，在暴露的硅/锗层上形成栅电极。

公开(公告)号：US09620589B2

公开(公告)日：2017-04-11

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

公开(公告)号：US09263270B2

公开(公告)日：2016-02-16

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/4763 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US20150287782A1

公开(公告)日：2015-10-08

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种方法包括提供半导体衬底，在半导体衬底上限定对应于纳米线的相对顶点的长度，去除半导体衬底的一部分以提供第一鳍结构和第二鳍结构，蚀刻第一腔 在所述第一侧附近沉积保护层，去除所述保护层的一部分以暴露所述半导体衬底的一部分，以及蚀刻所述第一和第二腔连通的所述暴露的半导体衬底处的第二腔。 第一鳍片结构和第二鳍片结构相邻，其中第一鳍片结构的长度对应于相对的顶点，并且具有第一侧面和第二侧面。

公开(公告)号：US20140264626A1

公开(公告)日：2014-09-18

申请号：US14174474

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Nicolas Sassiat ,  Jan Hoentschel ,  Martin Trentzsch ,  Carsten Grass

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7833

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract translation: 在一些方面，本公开提供了一种用于半导体器件的栅电极结构。 在本文的一些说明性实施例中，栅电极结构包括在半导体衬底的第一有源区上的第一高k电介质层和第一高k电介质层上的第二高k电介质层。 第一高k电介质层具有并入其中的金属物质，用于调节第一高k电介质层的功函数。

公开(公告)号：US20140256097A1

公开(公告)日：2014-09-11

申请号：US13785557

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a CMOS integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process.

Abstract translation: 提供了一种用于形成半导体器件的方法，其包括在半导体衬底的有源区域中提供栅极结构，其中所述栅极结构包括具有高k材料，栅极金属层和栅极电极层的栅极绝缘层， 形成与栅极结构相邻的侧壁间隔，之后进行氟注入工艺。 还提供了一种用于形成CMOS集成电路结构的方法，其包括提供具有第一有源区和第二有源区的半导体衬底，在第一有源区中形成第一栅极结构，在第二有源区中形成第二栅极结构， 其中每个栅极结构包括具有高k材料，栅极金属层和栅极电极层的栅极绝缘层，形成与第一和第二栅极结构中的每一个相邻的侧壁间隔，之后执行氟注入工艺。

公开(公告)号：US10886419B2

公开(公告)日：2021-01-05

申请号：US15913344

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

公开(公告)号：US09812573B1

公开(公告)日：2017-11-07

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US09460955B2

公开(公告)日：2016-10-04

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。