公开(公告)号：US09373690B2

公开(公告)日：2016-06-21

申请号：US14826466

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

公开(公告)号：US09905476B2

公开(公告)日：2018-02-27

申请号：US15412598

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/11 ,  H01L29/43 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

公开(公告)号：US09660027B2

公开(公告)日：2017-05-23

申请号：US14887572

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/7391 ,  H01L29/775

Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09553092B2

公开(公告)日：2017-01-24

申请号：US14738288

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

Abstract translation: 通过直接金属栅极图案化在栅极腔中形成多个栅极叠层部分，以提供具有不同阈值电压的FinFET。 通过在不同的栅堆叠部分中选择性地并入具有不同功函数的金属层来获得不同的阈值电压。

公开(公告)号：US20140187028A1

公开(公告)日：2014-07-03

申请号：US13732455

申请日：2013-01-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

IPC: H01L21/8238

CPC classification number: H01L21/823857

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

公开(公告)号：US20160240478A1

公开(公告)日：2016-08-18

申请号：US14623115

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer ,  Kriteshwar K. Kohli ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Keith Kwong Hon Wong

IPC: H01L23/525 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/5228 ,  H01L27/11206

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

Abstract translation: 用于形成使用钨硅的精密电阻器或e熔丝结构的方法。 通过将氮注入结构来改变钨硅层。

公开(公告)号：US09397199B1

公开(公告)日：2016-07-19

申请号：US14992209

申请日：2016-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Unoh Kwon ,  Siddarth A. Krishnan ,  Vijay Narayanan ,  Jeffrey Sleight

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/762 ,  H01L21/268 ,  H01L29/51 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/02252 ,  H01L21/02351 ,  H01L21/2686 ,  H01L21/28185 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/20 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66356 ,  H01L29/7391

Abstract: The disclosure generally relates to a method for forming multiple III-V Tunnel Field-Effect Transistors (III-V TFETs) microchips in which each TFET has a different threshold voltage (Vt) or work-function. In one embodiment of the disclosure, four TFETs are formed on a substrate. Each TFET has a source, drain and a gate electrode. Each gate electrode is then processed independently to provide a substantially different threshold voltage. Each TFET will have an intrinsic channel.

Abstract translation: 本发明一般涉及用于形成多个III-V隧道场效应晶体管（III-V TFET）微芯片的方法，其中每个TFET具有不同的阈值电压（Vt）或工作功能。 在本公开的一个实施例中，在衬底上形成四个TFET。 每个TFET都有源极，漏极和栅极。 然后，每个栅极电极被独立地处理以提供基本上不同的阈值电压。 每个TFET将具有固有通道。

公开(公告)号：US09397177B2

公开(公告)日：2016-07-19

申请号：US14088462

申请日：2013-11-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract translation: 形成半导体器件的方法包括在半导体衬底上形成第一和第二半导体结构。 第一半导体结构包括具有第一栅极长度的第一栅极沟道区，并且第二半导体结构包括具有大于第一栅极长度的第二栅极长度的第二栅极沟道区。 该方法还包括在第一栅极沟道区域中形成的第一栅极空隙和形成在第二栅极沟道区域处的第二栅极空穴中沉积功函数金属层。 该方法还包括在功函数金属层上沉积半导体掩模层，同时蚀刻位于第一和第二栅极沟道区的硅掩模层，以重新暴露第一和第二栅极空隙。 在第一和第二栅极空隙中沉积低电阻金属以形成低电阻金属栅极叠层。

公开(公告)号：US20170236780A1

公开(公告)日：2017-08-17

申请号：US15485657

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20170133278A1

公开(公告)日：2017-05-11

申请号：US15412598

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L27/11 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.