公开(公告)号：US09263541B2

公开(公告)日：2016-02-16

申请号：US14261559

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。

公开(公告)号：US20170125535A1

公开(公告)日：2017-05-04

申请号：US15272919

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L29/161 ,  H01L29/417 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/08 ,  H01L21/768

CPC classification number: H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US20160133716A1

公开(公告)日：2016-05-12

申请号：US14995956

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

公开(公告)号：US20150311308A1

公开(公告)日：2015-10-29

申请号：US14261559

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。

公开(公告)号：US10818599B2

公开(公告)日：2020-10-27

申请号：US16237685

申请日：2019-01-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/161 ,  H01L29/08 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US10347541B1

公开(公告)日：2019-07-09

申请号：US15962808

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  David Paul Brunco ,  Pei Liu ,  Shariq Siddiqui ,  Jinping Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.

公开(公告)号：US20180047824A1

公开(公告)日：2018-02-15

申请号：US15792206

申请日：2017-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L21/02 ,  H01L29/161 ,  H01L29/08 ,  H01L29/417 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L21/76843 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US20170199139A1

公开(公告)日：2017-07-13

申请号：US14992319

申请日：2016-01-11

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Lisa F. Edge ,  Gangadhara R. Muthinti ,  Shariq Siddiqui

IPC: G01N27/02 ,  G01N21/25

CPC classification number: G01N27/02 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/211 ,  G01N21/25 ,  G01N21/27 ,  G01N21/8422 ,  G01N21/9501 ,  G01N2021/3568 ,  G01N2021/4126 ,  G01N2201/129

Abstract: In an embodiment, a method comprises fitting a spectroscopic data of a layer in a layered structure to a dielectric function having a real part and an imaginary part; confirming that the dielectric function is physically possible; based on the dielectric function not being physically possible, repeating the fitting the spectroscopic data, or, based on the dielectric function being physically possible, defining an n degree polynomial to the dielectric function; determining a second derivative and a third derivative of the n degree polynomial; equating the second derivative to a first governing equation and the third derivative to a second governing equation and determining a constant of the first governing equation and the second governing equation; and based on the key governing equations, determining one or more of a band gap, a thickness, and a concentration of the layer.

公开(公告)号：US09570344B2

公开(公告)日：2017-02-14

申请号：US14752210

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal Kamineni ,  Nicholas Vincent Licausi ,  Shariq Siddiqui ,  Jeremy Austin Wahl

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/535

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract translation: 一种方法可以包括在半导体结构中形成接触沟槽，使得接触沟槽延伸到接触层，形成包括使用硬掩模层，并用牺牲材料层填充接触沟槽，牺牲材料层形成在触点上 形成。 半导体结构可以包括在接触层上的牺牲材料层。

公开(公告)号：US20160056033A1

公开(公告)日：2016-02-25

申请号：US14830131

申请日：2015-08-19

Applicant: The Regents of the University of California ,  GLOBALFOUNDRIES, Inc. ,  Applied Materials, Inc.

Inventor： Kasra Sardashti ,  Tobin Kaufman-Osborn ,  Tyler Kent ,  Andrew Kummel ,  Shariq Siddiqui ,  Bhagawan Sahu ,  Adam Brand ,  Naomi Yoshida

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/0206 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/306 ,  H01L29/66181 ,  H01L29/94

Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III_V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Abstract translation: 在栅极氧化物沉积之前对SiGe或Ge表面的表面预处理清洁SiGe或Ge表面以提供氢封端表面或硫钝化（或S-H）表面。 在25-200℃的范围内进行低温下的高介电常数氧化物的原子层沉积（ALD），形成氧化物层。 退火在升高的温度下进行。 在损伤敏感的III_V半导体表面上的氧化物沉积的方法在100-200℃的低温下用氢和TMA（三甲基铝）的循环脉冲进行表面的原位清洗。原子层沉积（ALD ）的高介电常数氧化物形成氧化物层。 退火在升高的温度下进行。 退火可以产生硅封端的界面。