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    Methods for Manufacturing Semiconductor Devices
    11.
    发明申请
    Methods for Manufacturing Semiconductor Devices 有权
    半导体器件制造方法

    公开(公告)号：US20140170837A1

    公开(公告)日：2014-06-19

    申请号：US14106699

    申请日：2013-12-13

    Applicant: IMEC

    Inventor： Benjamin Vincent ,  Geert Eneman

    IPC: H01L21/322

    CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

    Abstract translation: 公开了一种用于从有源层减少缺陷的方法。 有源层可以是半导体器件中的半导体的一部分。 有源层可以至少由隔离结构侧向限定，并且可以在接触界面物理地接触隔离结构。 隔离结构和有源层可以邻接在共同的基本平坦的表面上。 该方法可以包括在共同的基本上平坦的表面上提供图案化的应力诱导层。 应力诱导层可以适于在活性层中诱导应力场，并且感应应力场可能导致活性层中缺陷的剪切应力。 该方法还可以包括在将图案化的应力诱导层提供在共同的基本平坦的表面上之后执行退火步骤。 该方法可以另外包括从共同的基本平坦的表面去除图案化的应力诱导层。

    Method for Forming a Vertical Channel Device, and a Vertical Channel Device
    14.
    发明申请
    Method for Forming a Vertical Channel Device, and a Vertical Channel Device 审中-公开

    公开(公告)号：US20190081156A1

    公开(公告)日：2019-03-14

    申请号：US16119132

    申请日：2018-08-31

    Applicant: IMEC VZW

    Inventor： Anabela Veloso ,  Geert Eneman ,  Nadine Collaert ,  Erik Rosseel

    IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

    Abstract: A device and method for forming a vertical channel device is disclosed. The method includes: forming a vertical semiconductor pillar on a substrate, the vertical semiconductor pillar including a first pillar section, a second pillar section and a third pillar section, wherein the second pillar section is arranged between the first pillar section and the third pillar section and wherein the second pillar section is formed of a material being different from a material forming an upper portion of the first pillar section and different from a material forming a lower portion of the third pillar section; forming a spacer layer on a peripheral surface of the upper portion of the first pillar section and on a peripheral surface of the lower portion of the third pillar section; and forming a gate stack embedding the second pillar section and said upper portion of the first pillar section and said lower portion of the third pillar section, wherein the spacer layer forms a spacer between the gate stack and said upper portion of the first pillar section and between the gate stack and said lower portion of the third pillar section.

    Method for manufacturing a transistor device
    16.
    发明授权
    Method for manufacturing a transistor device 有权
    晶体管器件制造方法

    公开(公告)号：US09406777B2

    公开(公告)日：2016-08-02

    申请号：US14667376

    申请日：2015-03-24

    Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

    Inventor： Seung Hun Lee ,  Geert Eneman

    IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267

    CPC classification number: H01L29/66545 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions.

    Abstract translation: 公开了一种制造包括沟道层的晶体管器件的方法。 在一个实例中，该方法包括提供衬底，在衬底上外延生长应变层（无缺陷），外延生长外延生长的应变层上的沟道层，并在沟道层上提供栅极结构。 在该示例中，该方法还包括选择性地蚀刻到沟道层中并且至少部分地在外延生长的应变层中蚀刻，从而使用栅极结构作为掩模，从而产生从衬底延伸的突起。 突起可以包括沟道层的一部分和外延生长的应变层的至少上部，并且可以允许部分中的弹性松弛。

    Method for manufacturing transistor and associated device
    18.
    发明授权
    Method for manufacturing transistor and associated device 有权
    制造晶体管及相关器件的方法

    公开(公告)号：US09257539B2

    公开(公告)日：2016-02-09

    申请号：US14566073

    申请日：2014-12-10

    Applicant: IMEC VZW

    Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

    IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06

    CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

    Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

    Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

    METHOD FOR MANUFACTURING TRANSISTOR AND ASSOCIATED DEVICE
    19.
    发明申请
    METHOD FOR MANUFACTURING TRANSISTOR AND ASSOCIATED DEVICE 有权
    制造晶体管及相关器件的方法

    公开(公告)号：US20150179755A1

    公开(公告)日：2015-06-25

    申请号：US14566073

    申请日：2014-12-10

    Applicant: IMEC VZW

    Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

    Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

    Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

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