公开(公告)号：US20240088157A1

公开(公告)日：2024-03-14

申请号：US17942233

申请日：2022-09-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Sarah McTaggart ,  Aaron Vallett ,  Rajendran Krishnasamy ,  Megan Lydon-Nuhfer

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76286 ,  H01L21/84

Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.

公开(公告)号：US20230369314A1

公开(公告)日：2023-11-16

申请号：US17662921

申请日：2022-05-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Rajendran Krishnasamy ,  Anupam Dutta ,  Anindya Nath ,  Xiangxiang Lu ,  Satyasuresh Vvss Choppalli ,  Lin Lin

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0266

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

公开(公告)号：US20230178449A1

公开(公告)日：2023-06-08

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L29/732 ,  H01L23/373 ,  H01L29/417

CPC classification number: H01L23/367 ,  H01L29/7325 ,  H01L23/3736 ,  H01L29/41708

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

公开(公告)号：US11616127B2

公开(公告)日：2023-03-28

申请号：US17650854

申请日：2022-02-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Siva P. Adusumilli ,  Steven Bentley ,  Michael Joseph Zierak ,  Jeonghyun Hwang

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

公开(公告)号：US11424377B2

公开(公告)日：2022-08-23

申请号：US17065862

申请日：2020-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Ramsey Hazbun

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US11322639B2

公开(公告)日：2022-05-03

申请号：US16844606

申请日：2020-04-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  Ramsey Hazbun ,  Pernell Dongmo ,  Cameron E. Luce ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L31/107 ,  H01L31/18 ,  H01L31/028 ,  H01L31/0376

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

公开(公告)号：US20210376159A1

公开(公告)日：2021-12-02

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/763

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US11127816B2

公开(公告)日：2021-09-21

申请号：US16791214

申请日：2020-02-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Rajendran Krishnasamy ,  Steven M. Shank ,  Vibhor Jain

IPC: H01L29/08 ,  H01L29/49 ,  H01L29/16 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region.

公开(公告)号：US20240282852A1

公开(公告)日：2024-08-22

申请号：US18171765

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Kaustubh Shanbhag ,  Rajendran Krishnasamy ,  Judson R. Holt

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/0642 ,  H01L29/66681

Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.

公开(公告)号：US20240074167A1

公开(公告)日：2024-02-29

申请号：US17895156

申请日：2022-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Alain F. Loiseau

IPC: H01L27/112 ,  H01L23/525 ,  H01L29/735

CPC classification number: H01L27/11206 ,  H01L23/5256 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.