公开(公告)号：US20210141610A1

公开(公告)日：2021-05-13

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: G06F7/58 ,  H04L9/32 ,  H01L29/772 ,  H01L27/07 ,  H01L21/8234

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US20240339538A1

公开(公告)日：2024-10-10

申请号：US18749813

申请日：2024-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

公开(公告)号：US12094972B2

公开(公告)日：2024-09-17

申请号：US16406071

申请日：2019-05-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

公开(公告)号：US20210193573A1

公开(公告)日：2021-06-24

申请号：US16726497

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

公开(公告)号：US11101348B2

公开(公告)日：2021-08-24

申请号：US16044544

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Julien Frougier ,  Nigel G. Cave ,  Steven R. Soss ,  Daniel Chanemougame ,  Steven Bentley ,  Rohit Galatage ,  Bum Ki Moon

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/768 ,  H01L27/088 ,  B82Y40/00 ,  B82Y30/00

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

公开(公告)号：US20210135015A1

公开(公告)日：2021-05-06

申请号：US16668763

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Julien Frougier

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A gate electrode has a section that is wrapped about a first side surface and a second side surface of a mandrel that is composed of a dielectric material. A channel layer has a channel region that is positioned in part between the first side surface of the mandrel and the section of the gate electrode. The channel layer is composed of a two-dimensional material.

公开(公告)号：US20210083049A1

公开(公告)日：2021-03-18

申请号：US16574763

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Julien Frougier ,  Bradley Morgenfeld

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/786

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.

公开(公告)号：US10950610B2

公开(公告)日：2021-03-16

申请号：US16515913

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092

Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.

公开(公告)号：US11907685B2

公开(公告)日：2024-02-20

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: H04L9/32 ,  G06F7/58 ,  H04L9/08 ,  G06F21/00 ,  G06F21/73 ,  G06F21/72 ,  G06F21/76 ,  H01L21/02 ,  H01L27/088

CPC classification number: G06F7/588 ,  G06F21/00 ,  G06F21/72 ,  G06F21/73 ,  G06F21/76 ,  H01L21/02233 ,  H04L9/0866 ,  H04L9/3278 ,  H01L27/088 ,  H04L2209/12

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US11621269B2

公开(公告)日：2023-04-04

申请号：US16298413

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L27/11514 ,  H01L27/11502 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.