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    RADIX ENHANCEMENT FOR PHOTONIC PACKET SWITCH
    12.
    发明申请
    RADIX ENHANCEMENT FOR PHOTONIC PACKET SWITCH 有权
    用于光电分组开关的RADIX增强

    公开(公告)号：US20150373433A1

    公开(公告)日：2015-12-24

    申请号：US14764960

    申请日：2013-01-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Moray McLaren ,  Raymond G. Beausoleil ,  Norman Paul Jouppi ,  Marco Fiorentino ,  Alan Lynn Davis ,  Naveen Muralimanohar ,  Sheng Li

    IPC: H04Q11/00 ,  H04J14/02

    CPC classification number: H04Q11/0005 ,  H04J14/02 ,  H04Q11/0003 ,  H04Q11/0066 ,  H04Q11/0071 ,  H04Q2011/0016 ,  H04Q2011/002 ,  H04Q2011/0039

    Abstract: A system can include an optical multiplexer to combine a plurality of optical input signals having respective wavelengths into a wide-channel optical input signal that is provided to an input channel. The system also includes a photonic packet switch comprising a switch core and a plurality of ports defining a switch radix of the photonic packet switch. The input channel and an output channel can be associated with one of the plurality of ports. The photonic packet switch can process the wide-channel optical input signal and can generate a wide-channel optical output signal that is provided to the output channel. The system further includes an optical demultiplexer to separate the wide-channel optical output signal into a plurality of optical output signals having respective wavelengths. The optical multiplexer and the optical demultiplexer can collectively provide the system with a radix greater than the switch radix.

    Abstract translation: 系统可以包括光复用器以将具有各自波长的多个光输入信号组合成提供给输入通道的宽通道光输入信号。 该系统还包括光子分组交换机，其包括开关核心和限定光子分组交换机的开关基数的多个端口。 输入通道和输出通道可以与多个端口中的一个相关联。 光子分组交换机可以处理宽信道光输入信号，并可以产生提供给输出通道的宽信道光输出信号。 该系统还包括光解复用器，用于将宽信道光输出信号分离成具有各自波长的多个光输出信号。 光复用器和光解复用器可以向系统提供大于开关基数的基数。

    SYSTEM AND METHOD FOR DYNAMICALLY SELECTING BETWEEN MEMORY ERROR DETECTION AND ERROR CORRECTION
    14.
    发明申请
    SYSTEM AND METHOD FOR DYNAMICALLY SELECTING BETWEEN MEMORY ERROR DETECTION AND ERROR CORRECTION 审中-公开
    用于动态选择存储器错误检测和错误校正的系统和方法

    公开(公告)号：US20150248316A1

    公开(公告)日：2015-09-03

    申请号：US14431187

    申请日：2012-09-28

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Jeffrey C. Mogul ,  Naveen Muralimanohar ,  Mehul A. Shah ,  Eric A. Anderson

    IPC: G06F11/07

    CPC classification number: G06F11/073 ,  G06F11/0763 ,  G06F11/0793 ,  G06F11/1048 ,  G11C2029/0411

    Abstract: Example methods, systems, and apparatus to dynamically select between memory error detection and memory error correction are disclosed herein. An example system includes a buffer, to store a flag settable to a first value to indicate that a memory page is to store error protection information to detect but not correct errors in the memory page. The flag is settable to a second value to indicate that the error protection information is to detect and correct errors for the memory page. The example system includes a memory controller to receive a request based on the flag to enable error detection without correction for the memory page when the flag is set to the first value, and to enable error detection and correction for the memory page when the flag is set to the second value.

    Abstract translation: 本文公开了在存储器错误检测和存储器错误校正之间动态选择的示例性方法，系统和装置。 示例系统包括缓冲器，用于存储可设置为第一值的标志，以指示存储器页面存储错误保护信息以检测存储器页面中的错误，而不是错误。 该标志可设置为第二个值，以指示错误保护信息是检测和纠正存储器页面的错误。 示例系统包括存储器控制器，用于当标志被设置为第一值时，基于该标志来接收请求以启用错误检测而无需对存储器页进行校正，并且当该标志为标志位时，允许存储器页的错误检测和校正 设置为第二个值。

    GLOBAL ERROR CORRECTION
    16.
    发明申请
    GLOBAL ERROR CORRECTION 有权
    全球错误修正

    公开(公告)号：US20160139989A1

    公开(公告)日：2016-05-19

    申请号：US14899708

    申请日：2013-07-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Naveen Muralimanohar ,  Doe Hyun Yoon

    IPC: G06F11/10 ,  G06F12/08 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1012 ,  G06F11/108 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/281

    Abstract: A method that includes evaluating, with a controller, local error detection (LED) information in response to a first memory access operation is disclosed. The LED information is evaluated per cache line segment of data associated with a rank of a memory. The method further includes determining an error in at least one of the cache line segments based on an error detection code and determining whether global error correction (GEC) data for a first cache line associated with the at least one cache line segment is stored in a GEC cache in the controller. The method also includes correcting the first cache line associated with the at least one cache line segment based on the GEC data retrieved from the GEC cache in the controller without accessing GEC data from a memory.

    Abstract translation: 公开了一种方法，其包括响应于第一存储器访问操作，与控制器评估本地错误检测（LED）信息。 根据与存储器的等级相关联的数据的每个高速缓存线段来评估LED信息。 该方法还包括基于错误检测码确定至少一个高速缓存行段中的错误，并确定与至少一个高速缓存线段相关联的第一高速缓存行的全局纠错（GEC）数据是否存储在 GEC缓存在控制器中。 该方法还包括基于从控制器中的GEC高速缓存检索的GEC数据来校正与至少一个高速缓存线段相关联的第一高速缓存行，而不从存储器访问GEC数据。

    Memory error identification based on corrupted symbol patterns
    18.
    发明授权
    Memory error identification based on corrupted symbol patterns 有权
    基于损坏的符号模式的内存错误识别

    公开(公告)号：US08966348B2

    公开(公告)日：2015-02-24

    申请号：US13689814

    申请日：2012-11-30

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Doe Hyun Yoon ,  Jichuan Chang ,  Naveen Muralimanohar

    IPC: G06F11/00

    CPC classification number: G06F11/006 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/10

    Abstract: A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern.

    Abstract translation: 系统包括存储器控制器，缓冲器，将存储器控制器耦合到缓冲器的第一通道以及将缓冲器耦合到存储器的第二通道。 第一信道和第二信道是发送包括多个符号的码字。 基于存储器的数据访问从多个突发形成符号。 存储器控制器是基于码字的损坏符号模式来识别存储器错误。 存储器控制器根据损坏的符号图案，将芯片故障，第一通道的第一引脚故障和第二通道的第二引脚故障区别为存储器错误的类型。

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