利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

31 条记录 (耗时 0.033 秒)

    Integrated circuit with simultaneous fabrication of dual damascene via and trench
    12.
    发明授权
    Integrated circuit with simultaneous fabrication of dual damascene via and trench 有权
    集成电路，同时制造双镶嵌通孔和沟槽

    公开(公告)号：US06995087B2

    公开(公告)日：2006-02-07

    申请号：US10328512

    申请日：2002-12-23

    申请人： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

    发明人： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.

    摘要翻译： 集成电路制造方法包括提供基底，形成第一导体，形成第一阻挡层，形成第一介电层，形成掩模层。 该方法还包括在掩模层中形成第一通孔，在掩模层中形成第一沟槽开口，同时在掩模层下方的层中形成第二通孔，并形成穿过掩模层的第二沟槽开口， 在掩模层下面的层中并且同时在掩模层下方的另一层中形成第三通孔。 该方法还包括使用第三通孔开口和掩模层去除第一阻挡层以形成沟槽和通孔，以及用导体填充沟槽和通孔以形成与第一导体接触的沟槽和通孔导体。

    Method to fabricate aligned dual damascene openings
    13.
    发明授权
    Method to fabricate aligned dual damascene openings 有权
    制造对准双镶嵌开口的方法

    公开(公告)号：US07372156B2

    公开(公告)日：2008-05-13

    申请号：US11174805

    申请日：2005-07-05

    申请人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    发明人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    IPC分类号： H01L29/40

    CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

    摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

    摘要翻译： 对准的双镶嵌开口结构，包括以下。 具有形成在其上的金属结构的结构。 金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。 在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。 下通道开口与上沟槽开口连通。 其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

    Method to fabricate aligned dual damascene openings
    14.
    发明授权
    Method to fabricate aligned dual damascene openings 有权
    制造对准双镶嵌开口的方法

    公开(公告)号：US06967156B2

    公开(公告)日：2005-11-22

    申请号：US10690998

    申请日：2003-10-22

    申请人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    发明人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L29/06

    CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

    摘要： A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.

    摘要翻译： 一种形成对准的双镶嵌开口的方法，包括以下顺序步骤。 在金属结构上形成层叠。 层叠层按升序包括底蚀刻停止层; 下介电材料层; 中间蚀刻停止层; 中间介电材料层; 和上介电层。 图案化的掩模层形成在图案化的上介电层上，留下图案化的上介电层的暴露的相对部分。 使用图案化掩模层和上介电层的暴露部分作为掩模，将中介电材料层图案化以形成开口。 使用图案化的上电介质层作为掩模，同时对图案化的中间介电材料层进行图案化以形成初始上沟槽开口; 并且使用图案化掩模层和图案化的中间蚀刻停止层作为掩模的下部电介质材料层形成与前述上部沟槽开口对准的开口下部通孔。

    Method for corrosion prevention during planarization
    15.
    发明授权
    Method for corrosion prevention during planarization 有权
    平面化期间的防腐蚀方法

    公开(公告)号：US07947604B2

    公开(公告)日：2011-05-24

    申请号：US12019647

    申请日：2008-01-25

    申请人： Fan Zhang ,  Lup San Leong ,  Yong Kong Siew ,  Bei Chao Zhang

    发明人： Fan Zhang ,  Lup San Leong ,  Yong Kong Siew ,  Bei Chao Zhang

    IPC分类号： H01L21/302

    CPC分类号： B24B37/042 ,  B24B37/046

    摘要： The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.

    摘要翻译： 本发明涉及在平坦化或抛光过程中减少或完全防止Cu腐蚀。 在本发明的一个方面中，RF信号用于在抛光之后在晶片表面前建立负偏压以消除Cu +或Cu 2+迁移。 在本发明的另一方面，使用DC电压电源来建立负偏压。

    Apparatus and methods for cleaning and drying of wafers
    19.
    发明授权
    Apparatus and methods for cleaning and drying of wafers 有权
    用于清洗和干燥晶片的装置和方法

    公开(公告)号：US08177993B2

    公开(公告)日：2012-05-15

    申请号：US11556696

    申请日：2006-11-05

    申请人： Boon Meng Seah ,  Bei Chao Zhang ,  Raymond Joy ,  Shao Beng Law ,  John Sudijono ,  Liang Choo Hsia

    发明人： Boon Meng Seah ,  Bei Chao Zhang ,  Raymond Joy ,  Shao Beng Law ,  John Sudijono ,  Liang Choo Hsia

    IPC分类号： B44C1/22

    CPC分类号： H01L21/67028 ,  H01L21/67051 ,  H01L21/6708

    摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.

    摘要翻译： 用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。 第一歧管具有用于将化学品分配到基底上的多个喷嘴。 第二歧管连接到真空源和/或干燥空气/气体源。 第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

    Using refractory metal silicidation phase transition temperature points to control and/or calibrate RTP low temperature operation
    20.
    发明授权
    Using refractory metal silicidation phase transition temperature points to control and/or calibrate RTP low temperature operation 失效
    使用难熔金属硅化相变温度点来控制和/或校准RTP低温操作

    公开(公告)号：US06517235B2

    公开(公告)日：2003-02-11

    申请号：US09867560

    申请日：2001-05-31

    申请人： Zhong Yun Zhu ,  Rajneesh Jaiswal ,  Haznita Abd Karim ,  Bei Chao Zhang ,  Johnny Cham ,  Ravi Sankar Yelamanchi ,  Chee Kong Leong

    发明人： Zhong Yun Zhu ,  Rajneesh Jaiswal ,  Haznita Abd Karim ,  Bei Chao Zhang ,  Johnny Cham ,  Ravi Sankar Yelamanchi ,  Chee Kong Leong

    IPC分类号： G01K1700

    CPC分类号： G01K15/002

    摘要： A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems. The temperature point depend upon the type of refractory metal used and can range from about 200 to 800 ° C.

    摘要翻译： 描述了用于控制和/或校准快速热处理系统的方法。 包括其上具有难熔金属层的硅半导体衬底的一个或多个晶片在不同温度的RTP系统中被硅化。 测量晶片的片电阻均匀性，从而检测最高均匀点处的硅化相变温度点。 温度点用于校准或复位RTP系统。 包括其上具有难熔金属层的硅半导体衬底的多个晶片可以在多个快速热处理系统中的每一个中被硅化。 测量每个晶片的薄片电阻均匀性，从而通过每个RTP系统的最高薄层电阻均匀性来检测硅化相变温度点。 温度点用于匹配每个RTP系统的温度。 温度点取决于使用的难熔金属的类型，可以在约200至800℃的范围内