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33 条记录 (耗时 0.03 秒)

    Method for reducing pitch
    11.
    发明授权
    Method for reducing pitch 有权
    降低音调的方法

    公开(公告)号：US06774051B2

    公开(公告)日：2004-08-10

    申请号：US10170309

    申请日：2002-06-12

    申请人： Chia-Chi Chung ,  Henry Chung ,  Ming-Chung Liang ,  Jerry Lai

    发明人： Chia-Chi Chung ,  Henry Chung ,  Ming-Chung Liang ,  Jerry Lai

    IPC分类号： H01L2131

    CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139

    摘要： A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features. The first and second polymer layers can be formed using dielectric resolution enhancement coating techniques.

    摘要翻译： 公开了一种用于形成具有减小的尺寸间距或间距的导电特征的半导体结构的方法。 在光致抗蚀剂特征上形成第一聚合物层，以有助于将下面的第一介电层和导电层图案化成第一介电特征和导电特征。 然后在第一电介质之间和导电特征之间的空间中形成第二电介质特征，随后除去第一电介质特征。 然后在第二介电特征上形成第二聚合物层，使得第二聚合物层的部分覆盖与第二电介质特征相邻的导电特征的对应部分。 随后，使用第二聚合物层来图案化导电特征，从而去除未被聚合物层覆盖的导电特征部分并限定第二导电特征。 可以使用电介质分辨率增强涂覆技术形成第一和第二聚合物层。

    THREE-DIMENSIONAL MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    16.
    发明申请
    THREE-DIMENSIONAL MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    三维存储器结构及其制造方法

    公开(公告)号：US20050133883A1

    公开(公告)日：2005-06-23

    申请号：US10906779

    申请日：2005-03-07

    申请人： Erh-Kun Lai ,  Ming-Chung Liang

    发明人： Erh-Kun Lai ,  Ming-Chung Liang

    IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/06 ,  H01L29/00

    CPC分类号： H01L27/1021 ,  H01L21/8221 ,  H01L23/5252 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.

    摘要翻译： 提供三维记忆结构及其制造方法。 第一堆叠层形成在衬底上。 第一堆叠层从衬底向上包括n型多晶硅层，导电层，反熔丝和另一n型多晶硅层。 图案化第一堆叠层以形成第一堆叠电路。 此后，在第一堆叠电路上形成第二堆叠层。 第二堆叠层从第一堆叠电路向上包括p型多晶硅层，导电层，反熔丝和另一p型多晶硅。 图案化第二堆叠层以形成垂直于第一堆叠电路的第二堆叠电路。 重复上述步骤以在衬底上形成更多的堆叠电路，并因此产生三维结构。

    Method of forming via holes
    17.
    发明授权
    Method of forming via holes 有权
    形成通孔的方法

    公开(公告)号：US08895445B2

    公开(公告)日：2014-11-25

    申请号：US13228108

    申请日：2011-09-08

    申请人： Wen-Kuo Hsieh ,  Marowen Ng ,  Ming-Chung Liang ,  Hsin-Yi Tsai

    发明人： Wen-Kuo Hsieh ,  Marowen Ng ,  Ming-Chung Liang ,  Hsin-Yi Tsai

    IPC分类号： H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

    摘要： A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

    摘要翻译： 用于形成衬底上的互连结构的通路和沟槽的方法包括通过光刻胶层中的节距减小图案曝光，显影图案以去除通孔间距减小图案，使用聚合物气体部分地蚀刻光致抗蚀剂层以将图案重新形成为 小通孔形状，并蚀刻剩余的光致抗蚀剂层以延伸重塑图案。 重新成形的小通孔形状图案具有比在长方向上的通孔间距减小图案更小的间距。 对于具有每个具有两个通孔的通孔间距减小图案，图案具有花生形状。 在重新成形蚀刻操作期间，聚合物气体更多地沉积在夹入的中间部分中，同时允许在未切割的部分中进行向下蚀刻。

    METHOD AND APPARATUS OF FORMING A VIA
    18.
    发明申请
    METHOD AND APPARATUS OF FORMING A VIA 有权
    方法和装置形成一个威盛

    公开(公告)号：US20100308469A1

    公开(公告)日：2010-12-09

    申请号：US12478619

    申请日：2009-06-04

    申请人： Hsin-Yi Tsai ,  Chih-Hao Chen ,  Ming-Chung Liang ,  Chii-Ping Chen ,  Lai Chien Wen ,  Yuh-Jier Mii

    发明人： Hsin-Yi Tsai ,  Chih-Hao Chen ,  Ming-Chung Liang ,  Chii-Ping Chen ,  Lai Chien Wen ,  Yuh-Jier Mii

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.

    摘要翻译： 本公开提供一种半导体器件，其包括：衬底; 第一导电线，位于所述衬底上并且沿着第一轴线延伸，所述第一导电线具有第一长度和第一宽度，所述第一长度沿着所述第一轴线被测量; 第二导电线，位于第一导电线之上并沿着不同于第一轴的第二轴延伸，第二导线具有第二长度和第二宽度，第二长度沿第二轴线测量; 以及耦合所述第一和第二导线的通孔，所述通孔具有接触所述第二导电线的上表面和接触所述第一导线的下表面。 通孔在上表面具有大致直边，直边沿第二轴线延伸并与第二导线基本对准。