公开(公告)号：US08884297B2

公开(公告)日：2014-11-11

申请号：US13696865

申请日：2011-05-06

申请人： Sachiaki Tezuka ,  Yasuhiro Jinbo ,  Toshinari Sasaki ,  Hidekazu Miyairi ,  Yosuke Kanzaki ,  Masao Moriguchi

发明人： Sachiaki Tezuka ,  Yasuhiro Jinbo ,  Toshinari Sasaki ,  Hidekazu Miyairi ,  Yosuke Kanzaki ,  Masao Moriguchi

IPC分类号： H01L21/336 ,  H01L21/205 ,  H01L29/04 ,  H01L29/786 ,  H01L21/02 ,  C23C16/50 ,  C23C16/455 ,  C23C16/24 ,  H01L29/66

CPC分类号： H01L21/02513 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/50 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.

摘要翻译： 微晶硅膜的制造方法包括以下步骤：在第一条件下通过等离子体CVD法在绝缘膜上形成第一微晶硅膜; 以及在第二条件下在所述第一微晶硅膜上形成第二微晶硅膜。 作为供给到处理室的源气体，使用含有硅和含氢气体的沉积气体。 在第一条件下，将氢的流量设定为包含沉积气体的流量的50〜1000倍，处理室内的压力为67〜1333Pa。 在第二条件下，将氢的流量设定为包含沉积气体的流量的100〜2000倍，处理室内的压力为1333〜13332Pa。

公开(公告)号：US08709836B2

公开(公告)日：2014-04-29

申请号：US13175990

申请日：2011-07-05

申请人： Hidekazu Miyairi ,  Takafumi Mizoguchi

发明人： Hidekazu Miyairi ,  Takafumi Mizoguchi

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： An object is to provide a method for manufacturing a thin film transistor and a display device with reduced number of masks, in which adverse effects of optical current are suppressed. A manufacturing method comprises forming a stack including, from bottom to top, a light-blocking film, a base film, a first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; performing first etching on the whole thickness of the stack using a first resist mask formed over it; forming a gate electrode layer by side etching the first conductive film in a second etching; forming a second resist mask over the stack; and performing third etching down to the semiconductor film, and partially etching it, using the second resist mask to form a source and drain electrode layer, a source and drain region, and a semiconductor layer.

摘要翻译： 本发明的目的是提供一种制造薄膜晶体管的方法和减少数量的掩模的显示装置，其中抑制了光电流的不利影响。 一种制造方法，包括从底部到顶部形成包括遮光膜，基底膜，第一导电膜，第一绝缘膜，半导体膜，杂质半导体膜和第二导电膜的堆叠体; 使用形成在其上的第一抗蚀剂掩模对堆叠的整个厚度执行第一蚀刻; 在第二蚀刻中通过侧蚀刻所述第一导电膜形成栅极电极; 在堆叠上形成第二抗蚀剂掩模; 并且使用第二抗蚀剂掩模对半导体膜执行第三蚀刻并部分蚀刻，以形成源极和漏极电极层，源极和漏极区域以及半导体层。

公开(公告)号：US08637866B2

公开(公告)日：2014-01-28

申请号：US12490447

申请日：2009-06-24

申请人： Toshiyuki Isa ,  Yasuhiro Jinbo ,  Sachiaki Tezuka ,  Koji Dairiki ,  Hidekazu Miyairi ,  Shunpei Yamazaki ,  Takuya Hirohashi

发明人： Toshiyuki Isa ,  Yasuhiro Jinbo ,  Sachiaki Tezuka ,  Koji Dairiki ,  Hidekazu Miyairi ,  Shunpei Yamazaki ,  Takuya Hirohashi

IPC分类号： H01L29/72

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 至少在源区和漏区侧，薄膜晶体管包括作为缓冲层的半导体层，该半导体层含有氮并且包括在栅极绝缘层和源极和漏极区之间的非晶结构中的晶体区域。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US08569120B2

公开(公告)日：2013-10-29

申请号：US12617406

申请日：2009-11-12

申请人： Erika Takahashi ,  Takayuki Kato ,  Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Mitsuhiro Ichijo ,  Tomokazu Yokoi

发明人： Erika Takahashi ,  Takayuki Kato ,  Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Mitsuhiro Ichijo ,  Tomokazu Yokoi

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/50 ,  H01L27/1214 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

摘要： An object is to provide a method for manufacturing a thin film transistor having favorable electric characteristics, with high productivity. A gate electrode is formed over a substrate and a gate insulating layer is formed over the gate electrode. A first semiconductor layer is formed over the gate insulating layer by generating plasma using a deposition gas containing silicon or germanium, hydrogen, and a rare gas. Next, a second semiconductor layer including an amorphous semiconductor and a microcrystal semiconductor is formed in such a manner that the first semiconductor layer is partially grown as a seed crystal by generating plasma using a deposition gas containing silicon or germanium, hydrogen, and a gas containing nitrogen. Then, a semiconductor layer to which an impurity imparting one conductivity is added is formed and a conductive film is formed. Thus, a thin film transistor is manufactured.

摘要翻译： 本发明的目的在于提供一种制造具有良好的电特性，高生产率的薄膜晶体管的方法。 在基板上形成栅电极，在栅电极上形成栅极绝缘层。 通过使用包含硅或锗，氢气和稀有气体的沉积气体产生等离子体，在栅绝缘层上形成第一半导体层。 接下来，以这样的方式形成包括非晶半导体和微晶半导体的第二半导体层，使得通过使用包含硅或锗的沉积气体，氢气和含有气体的气体产生等离子体，将第一半导体层部分地生长为晶种 氮。 然后，形成添加有赋予一种导电性的杂质的半导体层，形成导电膜。 因此，制造薄膜晶体管。

公开(公告)号：US08563431B2

公开(公告)日：2013-10-22

申请号：US11840435

申请日：2007-08-17

申请人： Hidekazu Miyairi ,  Eiji Higa

发明人： Hidekazu Miyairi ,  Eiji Higa

IPC分类号： H01L21/44

CPC分类号： H01L27/1288 ,  H01L21/311 ,  H01L21/32139 ,  H01L27/1214

摘要： In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes using a photoresist and simplifying the process is provided, and the throughput is improved. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or a semiconductor layer is manufactured without using a lithography technique that uses a photoresist. The etching mask is formed of a stacked layer structure of a light absorption layer and an insulating layer utilizing laser ablation by laser beam irradiation through a photomask.

摘要翻译： 在半导体器件的制造工艺中，提供了使用光致抗蚀剂减少光刻处理的数量并简化工艺的制造技术，并提高了生产量。 在不使用使用光致抗蚀剂的光刻技术的情况下，制造用于形成诸如导电层或半导体层的被处理层的图案的蚀刻掩模。 蚀刻掩模由光吸收层和绝缘层的堆叠层结构形成，利用通过光掩模的激光束照射的激光烧蚀。

公开(公告)号：US08546810B2

公开(公告)日：2013-10-01

申请号：US12788343

申请日：2010-05-27

申请人： Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Hiromichi Godo ,  Takafumi Mizoguchi ,  Shinobu Furukawa

发明人： Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Hiromichi Godo ,  Takafumi Mizoguchi ,  Shinobu Furukawa

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L29/78621 ,  H01L29/04 ,  H01L29/66765

摘要： A thin film transistor in which an effect of photo current is small and an On/Off ratio is high is provided. In a bottom-gate bottom-contact (coplanar) thin film transistor, a channel formation region overlaps with a gate electrode, a first impurity semiconductor layer is provided between the channel formation region and a second impurity semiconductor layer which is in contact with a wiring layer. A semiconductor layer which serves as the channel formation region and the first impurity semiconductor layer preferably overlap with each other in a region where they overlap with the gate electrode. The first impurity semiconductor layer and the second impurity semiconductor layer preferably overlap with each other in a region where they do not overlap with the gate electrode.

摘要翻译： 提供其中光电流的作用小且开/关比高的薄膜晶体管。 在底栅底接触（共面）薄膜晶体管中，沟道形成区域与栅电极重叠，在沟道形成区域和与布线接触的第二杂质半导体层之间设置第一杂质半导体层 层。 用作沟道形成区域和第一杂质半导体层的半导体层优选在与栅电极重叠的区域中彼此重叠。 第一杂质半导体层和第二杂质半导体层优选在不与栅电极重叠的区域中彼此重叠。

公开(公告)号：US08471252B2

公开(公告)日：2013-06-25

申请号：US12535715

申请日：2009-08-05

申请人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

IPC分类号： H01L21/34 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L29/78621 ,  H01L29/7869

摘要： An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

摘要翻译： 一个实施例是包括交错（顶栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地提供具有比半导体层更高的载流子浓度的金属氧化物层作为源极和漏极电极层与半导体层之间的缓冲层，从而形成欧姆接触。

公开(公告)号：US08450158B2

公开(公告)日：2013-05-28

申请号：US13282650

申请日：2011-10-27

申请人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

发明人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

IPC分类号： H01L21/336 ,  H01L21/365

CPC分类号： H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  Y02A40/29

摘要： A seed crystal which includes mixed phase grains including an amorphous silicon region and a crystallite which is a microcrystal that can be regarded as a single crystal is formed on an insulating film by a plasma CVD method under a first condition that enables mixed phase grains having high crystallinity and high uniformity of grain sizes to be formed at a low density, and then a microcrystalline semiconductor film is formed to be stacked on the seed crystal by a plasma CVD method under a second condition that enables the mixed phase grains to grow to fill a space between the mixed phase grains.

摘要翻译： 在通过等离子体CVD法在绝缘膜上形成包含非晶硅区域的混合相晶粒和作为可以被认为是单晶的微晶的晶种的晶种，其中在第一条件下，使得具有高的 以低密度形成晶粒尺寸的结晶度和高均匀性，然后通过等离子体CVD法在微晶半导体膜上形成层叠在晶种上的第二条件，使得混合相晶粒生长以填充 混合相之间的间隙。

公开(公告)号：US08346497B2

公开(公告)日：2013-01-01

申请号：US10808499

申请日：2004-03-25

申请人： Hidekazu Miyairi ,  Hideyuki Ebine

发明人： Hidekazu Miyairi ,  Hideyuki Ebine

IPC分类号： G01N21/00

CPC分类号： H01L27/1285 ,  G01N21/9501 ,  G01N2021/8822 ,  H01L21/02675 ,  H01L21/2026 ,  H01L21/268 ,  H01L27/1214

摘要： The invention provides a method for testing a semiconductor film, a manufacturing method of a semiconductor film, a laser crystallization method, a laser crystallization device, and a laser crystallization system, for testing a laser crystallized semiconductor film, which require less time, have sufficient reliability, are excellent in cost management and applicable to mass production. In the method for testing a semiconductor film having an improved crystallinity by irradiating an energy light, the tested semiconductor film is photographed in a dark field digital image and then the luminance of the digital image is calculated by a computer in a constant direction for testing.

摘要翻译： 本发明提供了半导体膜的测试方法，半导体膜的制造方法，激光结晶方法，激光结晶装置和激光结晶系统，用于测试需要更少时间的激光晶体化半导体膜，具有足够的 可靠性，成本管理优良，适用于批量生产。 在通过照射能量光来测试具有改善的结晶度的半导体膜的方法中，将所测试的半导体膜在暗场数字图像中拍摄，然后由计算机以恒定方向计算数字图像的亮度进行测试。

公开(公告)号：US08304775B2

公开(公告)日：2012-11-06

申请号：US12716002

申请日：2010-03-02

申请人： Hidekazu Miyairi ,  Takeyoshi Watabe ,  Takashi Shimazu

发明人： Hidekazu Miyairi ,  Takeyoshi Watabe ,  Takashi Shimazu

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78669 ,  H01L27/1288 ,  H01L29/78678 ,  H01L29/78696 ,  H01L51/52

摘要： A thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, and impurity semiconductor layers which are in contact with part of the semiconductor layer and which form a source region and a drain region. The semiconductor layer includes a microcrystalline semiconductor layer formed on the gate insulating layer and a microcrystalline semiconductor region containing nitrogen in contact with the microcrystalline semiconductor layer. The thin film transistor in which off-current is small and on-current is large can be manufactured with high productivity.

摘要翻译： 薄膜晶体管包括覆盖栅电极的栅极绝缘层，与栅极绝缘层接触的半导体层和与半导体层的一部分接触并形成源极区域和漏极区域的杂质半导体层。 半导体层包括形成在栅极绝缘层上的微晶半导体层和含有与微晶半导体层接触的氮的微晶半导体区域。 可以以高生产率制造截止电流小且导通电流大的薄膜晶体管。