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公开(公告)号：US20160063148A1
公开(公告)日：2016-03-03
申请号：US14645928
申请日：2015-03-12
Applicant: Hitachi, Ltd.
Inventor： MASATO HAYASHI , Chihiro YOSHIMURA , Masanao YAMAOKA
CPC classification number: G06F17/5009 , G06N7/005 , G06N99/002 , G11C11/1659
Abstract: A semiconductor device that can simulate interactions between nodes of a large-scale interaction model and can be manufactured easily at inexpensive cost is suggested. The semiconductor device is provided with a plurality of semiconductor chips, each of which simulates interactions between nodes of an interaction model, and an inter-chip wire, wherein the plurality of semiconductor chips are used to simulate interactions between nodes of a single interaction model; each semiconductor chip includes: a plurality of element units, each of which retains values indicating the state of corresponding nodes and interaction coefficients and determines values indicating the next state of the corresponding nodes based on the retained values indicating the state of the nodes and each of the interaction coefficients and values of each of other nodes; and a connection unit that sends and receives some of the values indicating the state of the nodes, which are retained by a necessary element unit , via inter-chip wire to and from another semiconductor chip or sends and receives the values indicating state of the nodes, which are retained by the necessary element unit to and from the other semiconductor chip while sharing the inter-chip wire by means of time sharing.
Abstract translation: 建议可以模拟大规模交互模型的节点之间的相互作用并且可以以便宜的成本容易地制造的半导体装置。 半导体器件设置有多个半导体芯片，每个半导体芯片模拟交互模型的节点之间的交互和芯片间线，其中多个半导体芯片用于模拟单个交互模型的节点之间的交互; 每个半导体芯片包括：多个元件单元，每个元件单元保持指示对应节点和交互系数的状态的值，并且基于指示节点的状态的保留值来确定指示对应节点的下一状态的值， 每个其他节点的交互系数和值; 以及连接单元，其通过芯片间线路连接到另一半导体芯片并从另一半导体芯片发送并接收指示节点状态的一些值，所述值指示由必要元素单元保留的节点的状态，或者发送和接收指示节点的状态的值 ，其通过时间共享共享芯片间线，由必需的元件单元保持在另一个半导体芯片之上和从另一个半导体芯片保持。
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公开(公告)号：US20160062951A1
公开(公告)日：2016-03-03
申请号：US14641578
申请日：2015-03-09
Applicant: HITACHI, LTD.
Inventor： Chihiro YOSHIMURA , Masato HAYASHI , Masanao YAMAOKA
CPC classification number: G06F17/18 , G06F7/58 , G06F7/588 , G06F2207/58 , G06N7/005 , G06N99/002 , G11C11/16 , G11C19/02 , G11C19/08 , G11C19/0875 , G11C19/0883 , H03K19/20
Abstract: A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.
Abstract translation: 半导体器件包括多个自旋单元，其单独地包括被配置为存储Ising模型中的自旋值的存储器单元，被配置为存储来自在自旋上进行交互的相邻自旋的相互作用系数的存储单元，配置的存储单元 以存储旋转的外部磁场系数，以及配置为确定后续旋转状态的相互作用电路。 自旋单元分别包括随机数发生器，其被配置为向多个自旋单元提供随机数，并且在执行相互作用以产生自旋的后续状态时生成两个值或三个值的模拟系数的两值模拟系数 的自旋单位来自相邻旋转单元的自旋值，相互作用系数和外部磁场系数。
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公开(公告)号：US20140159041A1
公开(公告)日：2014-06-12
申请号：US14095859
申请日：2013-12-03
Applicant: Hitachi, Ltd.
Inventor： Masanao YAMAOKA , Kenichi OSADA
IPC: H01L21/66
CPC classification number: H01L22/30 , H01L23/50 , H01L23/5286 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes: a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction; a plurality of signal-line through vias that are connected to the first semiconductor substrate and transmit signals, which are output from the first circuit block, to a second circuit block formed on another second semiconductor substrate; and a plurality of power-supply through vias for supplying power to the first circuit block, and in the semiconductor device, the plurality of power-supply through vias are formed at edges of the first semiconductor substrate along the third and fourth sides and are formed in a plurality of rows in the first direction. Each circuit block has a power consuming mode in which power larger than the power consumption in a normal mode is consumed.
Abstract translation: 半导体器件包括：第一电路块，形成在第一半导体衬底上，第一和第二侧沿第一方向延伸，第三和第四侧沿与第一方向相交的第二方向延伸; 连接到第一半导体衬底并将从第一电路块输出的发射信号的多个信号线通孔传送到形成在另一第二半导体衬底上的第二电路块; 以及多个用于向第一电路块提供电力的通孔的供电通道，并且在半导体器件中，多个电源通孔沿着第三和第四侧形成在第一半导体衬底的边缘处，并且形成 在第一方向上的多行中。 每个电路块具有消耗大于正常模式的功耗的功率消耗模式。
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公开(公告)号：US20220129780A1
公开(公告)日：2022-04-28
申请号：US17429954
申请日：2019-03-29
Applicant: Hitachi, Ltd.
Inventor： Takuya OKUYAMA , Masanao YAMAOKA
Abstract: Searching for a ground state of an Ising model is performed so that a combinatorial optimization problem is efficiently solved. An information processing apparatus stores an energy function setting an interaction between an i-th spin of a first spin group and a j-th spin of a second spin group so that the i-th spin of the first spin group and the j-th spin of the second spin group have the same value in a ground state in an interaction relationship of an Ising model represented as a complete bipartite graph connecting N spins of the first spin group and of the second spin group, and searches for the ground state of the Ising model based on the energy function and information unique to the spins. The search for the ground state of the Ising model is performed by applying an algorithm of simulated annealing method to the above-mentioned energy function.
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公开(公告)号：US20220101099A1
公开(公告)日：2022-03-31
申请号：US17335283
申请日：2021-06-01
Applicant: HITACHI, LTD.
Inventor： Takashi OSHIMA , Norikatsu TAKAURA , Masanao YAMAOKA , Yoshitaka SASAGO
Abstract: According to one embodiment, provided is an information processing system including a parent device and a plurality of child devices. The child device constitutes at least a portion of at least one device selected from a function approximator and an annealing machine, each of the parent devices and the plurality of child devices include a communication interface, and the communication interface is at least one selected from a wireless communication interface and a wired communication interface including an analog circuit. Data to be processed by the child device is transmitted from the parent device to at least one of the plurality of child devices, and an output of at least one node of the child device is transmitted to at least one of the parent device and the other child devices.
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Patent Agency Ranking
公开(公告)号：US20180247691A1
公开(公告)日：2018-08-30
申请号：US15755257
申请日：2015-08-27
Applicant: HITACHI, LTD.
Inventor： Takuya OKUYAMA , Masanao YAMAOKA
CPC classification number: G11C11/419 , G06F7/00 , G06F7/588 , G06N7/005 , G06N99/00 , G11C7/1006 , G11C7/222 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675
Abstract: Provided are a semiconductor device and an information processing device that can be manufactured easily at low cost and can calculate an arbitrary interaction model such as an Ising model. A semiconductor device that performs a non-linear operation includes a memory, a reading unit that reads data from the memory, a majority circuit that inputs a result of a predetermined operation on the data read by the reading unit, and a write circuit that receives an output of the majority circuit, a value of a predetermined signal is stochastically inverted at a preceding stage of the majority circuit.
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公开(公告)号：US20170262226A1
公开(公告)日：2017-09-14
申请号：US15504127
申请日：2014-09-03
Applicant: HITACHI, LTD.
Inventor： Masanao YAMAOKA , Chihiro YOSHIMURA
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06N7/005 , G06N99/002
Abstract: A semiconductor integrated circuit apparatus 23 is used for obtaining an optimum solution using an Ising model, and the semiconductor integrated circuit apparatus 23 includes plural spin cells 1 that are connected with each other. Here, each spin cell 1 includes: a memory cell 9(N) for memorizing a spin value; a computing circuit 10 for computing interactions among the plural spin cells that are connected with each other; a memory circuit 4 for holding at least one-bit data; and an inversion logic circuit LG capable of modifying a computed result obtained by the computing circuit in accordance with data held by the memory circuit 4. The computed result modified by a modification circuit in accordance with the data held by the memory circuit is memorized in the memory cell 9(N) included in each spin cell 1.
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公开(公告)号：US20240232290A1
公开(公告)日：2024-07-11
申请号：US18368717
申请日：2023-09-15
Applicant: Hitachi, Ltd.
Inventor： Yusuke SUGITA , Nobuo BENIYAMA , Masanao YAMAOKA
Abstract: An object is to efficiently solve a quadratic programming problem having a k-hot constraint (k is a positive integer) for binary variables. A preferred aspect of the invention is an optimization method for, using an information processing apparatus, solving a quadratic programming problem in which one or more independent k-hot constraints are imposed on binary variables, the information processing apparatus including a processor, a storage device, an input device, and an output device. The information processing apparatus relaxes the binary variables into continuous values by adding correction values to a nonlinear coefficients of the binary variables on which the k-hot constraints are imposed, and the information processing apparatus executes a solution search while satisfying the k-hot constraints by executing a state transition such that a sum of a set of continuous variables on which the k-hot constraint is imposed is constant.
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公开(公告)号：US20220230252A1
公开(公告)日：2022-07-21
申请号：US17611946
申请日：2020-04-24
Applicant: HITACHI, LTD.
Inventor： Manabu SUGANUMA , Jun OGAWA , Masanao YAMAOKA , Takuya OKUYAMA
Abstract: [Problem] To efficiently generate multiple portfolio candidates based on investment policies of each financial institution and present the portfolio candidates to a user in an easily understandable form.
[Solution] A portfolio creation assistance device 100, includes: a storage unit 101 storing information on each of financial commodities; and a computation unit 104 performing a computation of an Ising model of a predetermined expression in which items of an expected return rate, a price drop risk, and a market sensitivity in a portfolio including combined predetermined ones of the financial commodities indicated by the information are combined with weights for the respective items, wherein the computation unit 104 outputs portfolios each obtained for one of patterns of the weights for the respective items as a result of the computation to a predetermined device, the portfolios each minimizing a value of the predetermined expression.-
公开(公告)号：US20190267065A1
公开(公告)日：2019-08-29
申请号：US16285549
申请日：2019-02-26
Applicant: Hitachi, Ltd.
Inventor： Masato HAYASHI , Masanao YAMAOKA
Abstract: The information processing apparatus is provided with a plurality of spin units for storing spin states and searching for a predetermined state by updating a spin state of a spin unit based on spin states of other spin units. The information processing apparatus includes: a first semiconductor integrated circuit device in which a plurality of first spin units are formed; a second semiconductor integrated circuit device in which a second spin unit is formed; an inter-chip wire connecting the first semiconductor integrated circuit device and the second semiconductor integrated circuit device; and a transmitter connection unit connected to the inter-chip wire and simultaneously shared by the plurality of first spin units. The transmitter connection unit transmits a spin state of a spin unit of which the spin state is changed among the plurality of first spin units, to the second semiconductor integrated circuit device through the inter-chip wire.
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