公开(公告)号：US11322390B2

公开(公告)日：2022-05-03

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L25/16 ,  H01L21/762 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US20210118724A1

公开(公告)日：2021-04-22

申请号：US16996413

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8249 ,  H01L27/07

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate. The method includes: (a) providing a SixGe1-x(100) substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the SixGe1-x(100) substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a SiyGe1-y(100) surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the SiyGe1-y(100) surface in the first region; (f) forming a trench in the second region which exposes the SixGe1-x(100) substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the SiyGe1-y(100) surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.

公开(公告)号：US10367031B2

公开(公告)日：2019-07-30

申请号：US15701743

申请日：2017-09-12

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L23/40 ,  H01L27/148 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L29/417 ,  H01L31/0216 ,  H01L21/8258 ,  B28D1/00 ,  H01L21/304 ,  H01L31/0224

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US20180076260A1

公开(公告)日：2018-03-15

申请号：US15701743

申请日：2017-09-12

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L27/148 ,  H01L31/0216 ,  H01L29/417

CPC classification number: H01L27/14875 ,  B28D1/005 ,  H01L21/304 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/0694 ,  H01L29/41708 ,  H01L31/02164 ,  H01L31/022408

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US20230200078A1

公开(公告)日：2023-06-22

申请号：US18065335

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Mihaela Ioana Popovici ,  Jan Van Houdt ,  Amey Mahadev Walke ,  Gouri Sankar Kar ,  Jasper Bizindavyi

IPC: H10B51/00 ,  H01L29/786 ,  H01L27/12 ,  C23C16/455

CPC classification number: H01L27/11585 ,  C23C16/45536 ,  H01L27/1222 ,  H01L28/60 ,  H01L29/7869

Abstract: Example embodiments relate to ferroelectric devices. An example ferroelectric device layer structure includes a first electrode. The ferroelectric device layer structure also includes a second electrode. Additionally, the ferroelectric device layer structure includes a ferroelectric layer of hafnium zirconate (HZO). Further, the ferroelectric device layer structure includes an oxide layer of Nb2O5 or Ta2O5 arranged on the ferroelectric layer. The ferroelectric layer and the oxide layer are arranged between the first electrode and the second electrode.

公开(公告)号：US11646200B2

公开(公告)日：2023-05-09

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02395 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02398 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US20200091003A1

公开(公告)日：2020-03-19

申请号：US16550085

申请日：2019-08-23

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters ,  Niamh Waldron ,  Robert Langer ,  Bernardette Kunert

IPC: H01L21/8258 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/308 ,  H01L21/3105

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

公开(公告)号：US20190273115A1

公开(公告)日：2019-09-05

申请号：US16419576

申请日：2019-05-22

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L27/148 ,  H01L27/06 ,  H01L21/768 ,  H01L29/417 ,  H01L31/0216 ,  H01L21/822

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US10347536B2

公开(公告)日：2019-07-09

申请号：US16203605

申请日：2018-11-28

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L27/02

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US10236183B2

公开(公告)日：2019-03-19

申请号：US15652786

申请日：2017-07-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert ,  Rita Rooyackers

IPC: H01L29/778 ,  H01L21/762 ,  H01L21/18 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L29/04 ,  H01L21/84 ,  H01L29/78 ,  H01L23/66

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.