公开(公告)号：US09741618B2

公开(公告)日：2017-08-22

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09704748B2

公开(公告)日：2017-07-11

申请号：US14751035

申请日：2015-06-25

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Roesner ,  Gudrun Stranzl ,  Rudolf Rothmaler

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  G03F1/38

CPC classification number: H01L21/78 ,  G03F1/38 ,  H01L21/3065 ,  H01L21/3083

Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.

公开(公告)号：US20170030890A1

公开(公告)日：2017-02-02

申请号：US15221010

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Gerald Holweg ,  Yonsuang Arnanthigo ,  Jan Berger ,  Guenter Denifl ,  Sylvicley Figueira Da Silva ,  Iris Moder ,  Thomas Ostermann ,  Alexander Oswatitsch ,  Vijaye Kumar Rajaraman ,  Gudrun Stranzl

IPC: G01N33/49 ,  B01D69/02 ,  B01D71/02 ,  B01D61/14

CPC classification number: G01N33/491 ,  B01D61/147 ,  B01D61/18 ,  B01D63/087 ,  B01D69/02 ,  B01D71/02 ,  B01D71/022 ,  B01D71/027 ,  B01D2313/345 ,  B01D2325/02 ,  B01D2325/26

Abstract: A microfiltration device comprises a substrate having a first surface and a second surface opposite to the first surface. The substrate includes a cavity between the first surface and the second surface. The substrate further includes a microfilter including a frame part in contact with the substrate and a filter part abutting the cavity. The microfilter comprises in both the frame part and the filter part a semiconducting or conducting material.

Abstract translation: 微滤装置包括具有第一表面和与第一表面相对的第二表面的基底。 衬底包括在第一表面和第二表面之间的空腔。 该基板还包括一个微型过滤器，它包括一个与该基板接触的框架部分和一个邻接腔体的过滤器部件。 微型过滤器在框架部分和过滤器部分中均包括半导体或导电材料。

公开(公告)号：US20150221523A1

公开(公告)日：2015-08-06

申请号：US14598288

申请日：2015-01-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/3213 ,  H01L21/283 ,  H01L27/02 ,  H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US20150217997A1

公开(公告)日：2015-08-06

申请号：US14170187

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

Abstract translation: 公开了一种用于构造衬底和结构化衬底的方法。 在一个实施方案中，一种方法包括提供具有第一主表面和第二主表面的基底，其中所述基底固定到第二主表面处的载体布置，在所述基底的第一主表面处执行光刻步骤以标记 在第一主表面处的多个位置，对应于未来穿孔结构的多个部位以及从基板获得的多个未来单个半导体芯片的未来切割区域，以及在多个位置等离子体蚀刻基板，直到载体 从而在多个单独的半导体芯片内形成穿孔结构，同时沿着切口区分离各个半导体芯片。

公开(公告)号：US20150064879A1

公开(公告)日：2015-03-05

申请号：US14013822

申请日：2013-08-29

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01L21/78 ,  B28D5/00 ,  H01J37/32

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract translation: 提供了关于将基板分离成多个部件的各种方法和装置。 例如，首先进行部分分离，然后将部分分离的基板完全分离成多个部分。

公开(公告)号：US20140235035A1

公开(公告)日：2014-08-21

申请号：US14260903

申请日：2014-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底中形成开口。 该方法包括在开口内形成虚拟填充材料并使衬底变薄以暴露虚拟填充材料。 去除虚拟填充材料。

公开(公告)号：US11063014B2

公开(公告)日：2021-07-13

申请号：US16413195

申请日：2019-05-15

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl

IPC: H01L23/00 ,  H01L29/45

Abstract: A semiconductor device includes a silicon layer, a metal silicide layer arranged directly on the silicon layer, and a solder layer arranged directly on the metal silicide layer.

公开(公告)号：US20180315713A1

公开(公告)日：2018-11-01

申请号：US16029934

申请日：2018-07-09

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/3065

Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.

公开(公告)号：US10020264B2

公开(公告)日：2018-07-10

申请号：US14698639

申请日：2015-04-28

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  G06K7/14

CPC classification number: H01L23/544 ,  H01L21/30655 ,  H01L21/78 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54473

Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.