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    Memory devices and methods for operating the same
    11.
    发明授权
    Memory devices and methods for operating the same 有权

    公开(公告)号：US11907044B2

    公开(公告)日：2024-02-20

    申请号：US17473905

    申请日：2021-09-13

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Wolf Allers

    IPC: G06F11/00 ,  G11C7/06 ,  G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/004 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/06

    Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

    System and method for adaptive bit rate programming of a memory device
    14.
    发明授权
    System and method for adaptive bit rate programming of a memory device 有权
    用于存储器件的自适应比特率编程的系统和方法

    公开(公告)号：US09032140B2

    公开(公告)日：2015-05-12

    申请号：US13751883

    申请日：2013-01-28

    Applicant: Infineon Technologies AG

    Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

    IPC: G11C16/10 ,  G06F12/02 ,  G11C16/06 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

    Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

    Electronic Device with a Plurality of Memory Cells and with Physically Unclonable Function
    15.
    发明申请
    Electronic Device with a Plurality of Memory Cells and with Physically Unclonable Function 有权
    具有多个存储单元和具有物理不可克隆功能的电子设备

    公开(公告)号：US20140126306A1

    公开(公告)日：2014-05-08

    申请号：US13668963

    申请日：2012-11-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Jan Otterstedt ,  David Müller

    IPC: G11C7/06

    CPC classification number: G11C7/06 ,  G11C16/22 ,  H04L9/0841 ,  H04L9/3263 ,  H04L63/0823

    Abstract: An electronic device includes a non-volatile memory having a plurality of memory cells, a memory controller, and an evaluator. The memory controller is configured to provide control signals to the non-volatile memory causing the non-volatile memory, or a selected memory section of the non-volatile memory, to be in one of a read state and a weak erase state, wherein the weak erase state causes the plurality of memory cells to maintain different states depending on different physical properties of the plurality of memory cells. The evaluator is configured to read out the plurality of memory cells and to provide a readout pattern during the read state, wherein the readout pattern that is provided after a preceding weak erase state corresponds to a physically unclonable function (PUF) response of the electronic device uniquely identifying the electronic device.

    Abstract translation: 电子设备包括具有多个存储单元的非易失性存储器，存储器控制器和评估器。 存储器控制器被配置为向非易失性存储器提供控制信号，使得非易失性存储器或非易失性存储器的所选存储器部分处于读取状态和弱擦除状态之一，其中， 弱擦除状态导致多个存储单元根据多个存储单元的不同物理特性来维持不同的状态。 评估器被配置为读出多个存储器单元并且在读取状态期间提供读出模式，其中在先前的弱擦除状态之后提供的读出模式对应于电子设备的物理不可克隆功能（PUF）响应 唯一地识别电子设备。

    Chip and method for detecting an attack on a chip
    19.
    发明授权
    Chip and method for detecting an attack on a chip 有权

    公开(公告)号：US09679167B2

    公开(公告)日：2017-06-13

    申请号：US14080847

    申请日：2013-11-15

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Thomas Kuenemund

    IPC: G06F21/00 ,  G06F21/87

    CPC classification number: G06F21/87

    Abstract: According to one embodiment, a chip is described comprising a substrate; an energy source configured to provide energy to the substrate; an energy receiver configured to receive energy from the energy source via the substrate and a determiner configured to determine a value of a parameter of the energy transmission between the energy source and the energy receiver, to check whether the value matches a predetermined value of the parameter and to output a signal depending on the result of the check.

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