公开(公告)号：US20140198583A1

公开(公告)日：2014-07-17

申请号：US13743409

申请日：2013-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Nirschl

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.

Abstract translation: 实施例涉及包括多个非易失性存储器元件的系统和方法，其中至少两个非易失性存储器元件的集合共享一个选择元件，用于选择用于读取操作的非易失性存储器元件组中的特定一个的非易失性存储器元件之一， 一个程序操作。

公开(公告)号：US20140133250A1

公开(公告)日：2014-05-15

申请号：US14160784

申请日：2014-01-22

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Thomas Nirschl

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18

Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Abstract translation: 本公开的一些实施例涉及促进快速和准确的读取操作的读出放大器架构。 感测放大器架构包括用于其第一读出放大器级的折叠共源共栅放大器和用于为感测放大器的感测线和参考感测线建立预充电状态的预充电电路。 预充电电路和折叠共源共栅放大器各自包括相同尺寸的一个或多个共源共栅晶体管，并且在其栅极上接收相同的偏置电压。 该架构在相对较小的占地面积中提供快速准确的读取操作，从而提供了成本和性能的良好组合。

公开(公告)号：US20140124827A1

公开(公告)日：2014-05-08

申请号：US14153947

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract translation: 集成电路装置，其包括场效应晶体管，特别是隧道场效应晶体管。 特别地，对于具有较厚的栅极电介质的隧道场效应晶体管与相同的集成电路装置上的其它晶体管相比较的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域之间的界面。

公开(公告)号：US09219063B2

公开(公告)日：2015-12-22

申请号：US14153947

申请日：2014-01-13

Applicant: Infineon Technologies AG

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/088 ,  H01L29/739 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/105 ,  H01L21/336 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract translation: 集成电路装置，其包括场效应晶体管，特别是隧道场效应晶体管。 特别地，对于具有较厚的栅极电介质的隧道场效应晶体管与相同的集成电路装置上的其它晶体管相比较的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域之间的界面。

公开(公告)号：US09153293B2

公开(公告)日：2015-10-06

申请号：US13690299

申请日：2012-11-30

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jan Otterstedt ,  Alexander Duch

IPC: G11C29/00 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C7/00 ,  G11C16/0425 ,  G11C16/3427 ,  G11C16/349

Abstract: A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted.

Abstract translation: 操作集成电路的方法包括确定至少一个存储器单元的至少一个特性并对至少一个存储单元进行操作，其中基于所确定的至少一个特征来确定至少一个附加存储器单元的干扰 调整。

公开(公告)号：US20150052387A1

公开(公告)日：2015-02-19

申请号：US13966679

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Nirschl

IPC: G11B20/18 ,  G06F11/16

CPC classification number: G11B20/1883 ,  G06F11/1048 ,  G06F11/1666 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52

Abstract: A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts.

Abstract translation: 公开了一种具有灵活读取参考的存储器系统。 该系统包括一个内存分区，一个故障计数组件和一个控制器。 存储器分区包括多个存储单元。 故障计算组件被配置为响应于内存分区的读取操作生成故障计数。 控制器被配置为通过利用故障计数来校准存储器分区的参考值。

公开(公告)号：US09343179B2

公开(公告)日：2016-05-17

申请号：US14132053

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Kern ,  Thomas Liebermann

IPC: G11C29/00 ,  G11C29/02 ,  G06F11/10

CPC classification number: G11C29/024 ,  G06F11/1076

Abstract: A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.

Abstract translation: 公开了一种执行三次扫描以测试地址解码器和字线驱动电路的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标​​电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。

公开(公告)号：US09240225B2

公开(公告)日：2016-01-19

申请号：US14160784

申请日：2014-01-22

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Thomas Nirschl

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18

Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Abstract translation: 本公开的一些实施例涉及促进快速和准确的读取操作的读出放大器架构。 感测放大器架构包括用于其第一读出放大器级的折叠共源共栅放大器和用于为感测放大器的感测线和参考感测线建立预充电状态的预充电电路。 预充电电路和折叠共源共栅放大器各自包括相同尺寸的一个或多个共源共栅晶体管，并且在其栅极上接收相同的偏置电压。 该架构在相对较小的占地面积中提供快速准确的读取操作，从而提供了成本和性能的良好组合。

公开(公告)号：US20150179270A1

公开(公告)日：2015-06-25

申请号：US14641496

申请日：2015-03-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Nirschl

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.

Abstract translation: 实施例涉及包括多个非易失性存储器元件的系统和方法，其中至少两个非易失性存储器元件的集合共享一个选择元件，用于选择用于读取操作的非易失性存储器元件组中的特定一个的非易失性存储器元件之一， 一个程序操作。

公开(公告)号：US20150170762A1

公开(公告)日：2015-06-18

申请号：US14132053

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Kern ,  Thomas Liebermann

IPC: G11C29/02 ,  G06F11/10

CPC classification number: G11C29/024 ,  G06F11/1076

Abstract: The disclosure relates to systems and methods for performing a word line address scan in a semiconductor memory. More specifically, the disclosure provides a system and method for performing three scans for testing address decoder and word line drive circuits. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected. The present disclosure may realize all three scans or a combination of the three scans.

Abstract translation: 本公开涉及用于在半导体存储器中执行字线地址扫描的系统和方法。 更具体地，本公开提供了一种用于对地址解码器和字线驱动电路进行三次扫描的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标​​电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。 本公开可以实现所有三个扫描或三个扫描的组合。