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    ELECTRONIC DEVICE, ELECTRONIC SYSTEM, METHOD FOR OPERATING AN ELECTRONIC DEVICE, AND METHOD FOR OPERATING AN ELECTRONIC SYSTEM
    1.
    发明公开
    ELECTRONIC DEVICE, ELECTRONIC SYSTEM, METHOD FOR OPERATING AN ELECTRONIC DEVICE, AND METHOD FOR OPERATING AN ELECTRONIC SYSTEM 审中-公开

    公开(公告)号：US20240134743A1

    公开(公告)日：2024-04-25

    申请号：US18489245

    申请日：2023-10-17

    Applicant: Infineon Technologies AG

    Inventor： Jens Barrenscheen ,  Jens Rosenbusch

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F11/1004

    Abstract: An electronic device including a functional unit, a storage unit, and a data transmission apparatus. The functional unit provides a function to a superordinate electronic apparatus. The data transmission apparatus transmits data from the storage unit to the functional unit. The storage unit includes a plurality of memory cells and an error correction unit configured to generate a set of correction data for a set of payload data, to store the set of correction data in the memory cells, to read the set of payload data and the set of correction data from the memory cells in response to an individual read request from the data transmission apparatus, to correct the set of payload data and the set of correction data using the set of correction data, and to make both the corrected payload data and the corrected correction data available for the data transmission apparatus.

    ELECTRONIC DEVICE
    3.
    发明申请
    ELECTRONIC DEVICE 有权

    公开(公告)号：US20240380409A1

    公开(公告)日：2024-11-14

    申请号：US18659418

    申请日：2024-05-09

    Applicant: Infineon Technologies AG

    Inventor： Wei Wang ,  Thiyagu Loganathan ,  Henning Behrmann ,  Jörg Schreiner ,  Jens Rosenbusch ,  Rocco Calabro

    IPC: H03M1/12

    Abstract: According to various embodiments, an electronic device is described, comprising a device input for connecting an analog signal source, an analog-to-digital converter having an analog-to-digital converter input connected to the device input, an alternating current source configured to supply an alternating current to the analog-to-digital-converter input and a detection circuit configured to store a reference for an amplitude of a voltage signal at the analog-to-digital-converter input caused by the alternating current, receive an output of the analog-to-digital converter, determine the amplitude of the voltage signal at the analog-to-digital-converter input caused by the alternating current by filtering the output of the analog-to-digital converter and output an error signal if the reference for the amplitude differs from the determined amplitude by more than a predetermined threshold.

    Data processing device and method for transmitting data over a bus
    6.
    发明授权
    Data processing device and method for transmitting data over a bus 有权

    公开(公告)号：US11995015B2

    公开(公告)日：2024-05-28

    申请号：US17684634

    申请日：2022-03-02

    Applicant: Infineon Technologies AG

    Inventor： Ning Chen ,  Jens Rosenbusch

    IPC: G06F13/362 ,  H04L9/32

    CPC classification number: G06F13/362 ,  H04L9/3278

    Abstract: Systems, methods, circuits, and devices for data protection are provided. In one example, a data processing device incudes a Physical Unclonable Function (PUF) source that is configured to generate PUF values, a bus, a plurality of bus access components that are configured to access the bus, and a masking information generation circuit. The masking information generation circuit is configured to generate masking information for at least one pair of bus access components using at least one PUF value and to transmit said information to the bus access components. The pair is configured in such a way that one bus access component masks the data according to the masking information generated for the pair before the data is sent over the bus and the other bus access component de-masks the data received over the bus according to the masking information generated for the pair.

    Execute in place architecture with integrity check
    7.
    发明授权
    Execute in place architecture with integrity check 有权

    公开(公告)号：US11640332B1

    公开(公告)日：2023-05-02

    申请号：US17502300

    申请日：2021-10-15

    Applicant: Infineon Technologies AG

    Inventor： Sunanda Manjunath ,  Jens Rosenbusch

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/07

    Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.

    INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, METHOD FOR OPERATING AN INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, MULTI-CORE PROCESSOR DEVICE AND METHOD FOR OPERATING A MULTI-CORE PROCESSOR DEVICE
    8.
    发明申请
    INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, METHOD FOR OPERATING AN INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, MULTI-CORE PROCESSOR DEVICE AND METHOD FOR OPERATING A MULTI-CORE PROCESSOR DEVICE 有权

    公开(公告)号：US20210263099A1

    公开(公告)日：2021-08-26

    申请号：US17179955

    申请日：2021-02-19

    Applicant: Infineon Technologies AG

    Inventor： Daniel Tille ,  Heiko Ahrens ,  Jens Rosenbusch

    IPC: G01R31/3177

    Abstract: An integrated circuit with self-test circuit is provided. The integrated circuit includes at least one logic circuit, at least one input storage element for storing work data, at least one output storage element, an input test storage element for storing test data, and at least one output test storage element, wherein the logic circuit is selectively connected to the input storage element on the input side, such that the input storage element provides the work data to the logic circuit, or is connected to the input test storage element on the input side, such that the input test storage element provides the test data to the logic circuit, wherein the logic circuit is further connected to the output storage element and the output test storage element on the output side, such that the logic circuit feeds data to the output storage element and/or to the output test storage element, and wherein the output storage element is configured to process the data from the logic circuit if the work data are provided to the logic circuit, and not to process the data from the logic circuit if the test data are provided to the logic circuit.

    Resistive memory transition monitoring
    9.
    发明授权
    Resistive memory transition monitoring 有权

    公开(公告)号：US10311955B2

    公开(公告)日：2019-06-04

    申请号：US16058552

    申请日：2018-08-08

    Applicant: Infineon Technologies AG

    Inventor： Ulrich Backhausen ,  Giacomo Curatolo ,  Jens Rosenbusch

    IPC: G11C11/00 ,  G11C13/00 ,  G01R31/12 ,  G01R31/14 ,  G11C29/02 ,  G11C29/50

    Abstract: A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The method includes determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; performing, by the control circuit, a predetermined action if the control circuit determination is positive; and storing, in a memory, the determined cell current at predetermined times, and to store the determined cell current change rate.

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