公开(公告)号：US20170200666A1

公开(公告)日：2017-07-13

申请号：US15292554

申请日：2016-10-13

Applicant: Infineon Technologies AG

Inventor： Wolfram Hable ,  Martin Gruber ,  Juergen Hoegerl

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H02M5/297 ,  H02M3/158 ,  H02M7/217 ,  H02M7/537 ,  H02M5/293 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/3735 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H02M3/158 ,  H02M5/293 ,  H02M5/297 ,  H02M7/003 ,  H02M7/217 ,  H02M7/537 ,  H01L2224/45099

Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.

公开(公告)号：US09589922B2

公开(公告)日：2017-03-07

申请号：US14214962

申请日：2014-03-16

Applicant: Infineon Technologies AG

Inventor： Christian Neugirg ,  Andreas Grassmann ,  Wolfram Hable ,  Ottmar Geitner ,  Frank Winter ,  Alexander Schwarz ,  Inpil Yoo

IPC: H01L23/373 ,  H01L23/00

CPC classification number: H01L23/3733 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/373 ,  H01L23/49833 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/40137 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.

Abstract translation: 提供一种电子模块，其包括第一载体; 电子芯片，其包括至少一个电子部件并且布置在所述第一载体上; 间隔元件，包括布置在所述电子芯片上并与所述至少一个电子部件导热连接的表面; 布置在间隔元件上的第二载体; 以及至少部分地包围所述电子芯片和所述间隔元件的模具化合物; 其中所述间隔元件包括具有与至少一个其它CTE匹配的CTE值的材料。

公开(公告)号：US20140197552A1

公开(公告)日：2014-07-17

申请号：US13742456

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US20220115293A1

公开(公告)日：2022-04-14

申请号：US17557168

申请日：2021-12-21

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/42 ,  H01L23/495 ,  H01L23/552 ,  H01L23/373 ,  H01L23/473

Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

公开(公告)号：US11244886B2

公开(公告)日：2022-02-08

申请号：US15710852

申请日：2017-09-21

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/42 ,  H01L23/495 ,  H01L23/552 ,  H01L23/373 ,  H01L23/473 ,  H01L23/00 ,  H01L23/31

Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.

公开(公告)号：US10283432B2

公开(公告)日：2019-05-07

申请号：US16111606

申请日：2018-08-24

Applicant: Infineon Technologies AG

Inventor： Mark Pavier ,  Wolfram Hable ,  Angela Kessler ,  Michael Sielaff ,  Anton Pugatschow ,  Charles Rimbert-Riviere ,  Marco Sobkowiak

IPC: H01L21/48 ,  H01L23/373 ,  B60R16/02 ,  H01L21/56 ,  H01L25/18 ,  H01L23/29 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L23/31

Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.

公开(公告)号：US10128165B2

公开(公告)日：2018-11-13

申请号：US15796771

申请日：2017-10-28

Applicant: Infineon Technologies AG

Inventor： Wolfram Hable ,  Andreas Grassmann ,  Juergen Hoegerl ,  Eduard Knauer ,  Michael Ledutke

IPC: H01L23/28 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L25/00 ,  B60L11/18 ,  H02M7/00

Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.

公开(公告)号：US10079195B2

公开(公告)日：2018-09-18

申请号：US15292554

申请日：2016-10-13

Applicant: Infineon Technologies AG

Inventor： Wolfram Hable ,  Martin Gruber ,  Juergen Hoegerl

IPC: H01L23/12 ,  H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H02M3/158 ,  H02M5/293 ,  H02M5/297 ,  H02M7/217 ,  H02M7/537

CPC classification number: H01L23/3735 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H02M3/158 ,  H02M5/293 ,  H02M5/297 ,  H02M7/003 ,  H02M7/217 ,  H02M7/537 ,  H01L2224/45099

Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.

公开(公告)号：US09397018B2

公开(公告)日：2016-07-19

申请号：US13742456

申请日：2013-01-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/373 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/06 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US09275926B2

公开(公告)日：2016-03-01

申请号：US13886284

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Wolfram Hable ,  Andreas Grassmann ,  Frank Winter ,  Ottmar Geitner ,  Alexander Schwarz ,  Alexander Herbrandt ,  Lothar Koenig ,  Andre Uhlemann

IPC: H01L23/34 ,  H01L21/50 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433 ,  H01L23/467 ,  H01L23/473 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/467 ,  H01L23/473 ,  H01L24/33 ,  H01L24/36 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/40137 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/37599

Abstract: According to an exemplary embodiment, a power module is provided which comprises a semiconductor chip, a bonding substrate comprising an electrically conductive sheet and an electric insulator sheet which is directly attached to the electrically conductive sheet and which is thermally coupled to the semiconductor chip, and an array of cooling structures directly attached to the electrically conductive sheet and configured for removing heat from the semiconductor chip when interacting with cooling fluid.

Abstract translation: 根据示例性实施例，提供了一种功率模块，其包括半导体芯片，包括导电片的接合衬底和直接附接到导电片并且热耦合到半导体芯片的电绝缘片，以及 直接连接到导电片的冷却结构的阵列，并被配置为当与冷却流体相互作用时从半导体芯片移除热量。