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    Zero-misalignment two-via structures
    14.
    发明授权
    Zero-misalignment two-via structures 有权

    公开(公告)号：US11694951B2

    公开(公告)日：2023-07-04

    申请号：US17537406

    申请日：2021-11-29

    Applicant: Intel Corporation

    Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings ,  Johanna Swan

    IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5386

    Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

    MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS
    18.
    发明申请
    MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS 有权

    公开(公告)号：US20220319996A1

    公开(公告)日：2022-10-06

    申请号：US17842600

    申请日：2022-06-16

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

    IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

    INTER-COMPONENT MATERIAL IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING
    20.
    发明申请
    INTER-COMPONENT MATERIAL IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING 有权

    公开(公告)号：US20220189839A1

    公开(公告)日：2022-06-16

    申请号：US17122167

    申请日：2020-12-15

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Aleksandar Aleksov

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components. In some embodiments, the liner material, the inorganic fill material, and a material of the third microelectronic component may include a thermally conductive material.

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