公开(公告)号：US12184751B2

公开(公告)日：2024-12-31

申请号：US17341150

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Jihwan Kim ,  Kai Yu ,  Gurmukh Singh ,  Stephen Kim ,  Richard Packard ,  Frank O'Mahony

IPC: H04L7/033 ,  H03K5/135 ,  H03L7/087 ,  H04L7/00

Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

公开(公告)号：US20220171718A1

公开(公告)日：2022-06-02

申请号：US17338479

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Jihwan Kim ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Frank O'Mahony

IPC: G06F13/16 ,  H03K19/20 ,  H03K17/687 ,  G06F13/42 ,  G06F1/04

Abstract: A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.

公开(公告)号：US10079648B2

公开(公告)日：2018-09-18

申请号：US15457588

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Tzu-Chien Hsueh ,  Frank O'Mahony

IPC: H04B15/00 ,  H04B17/10 ,  H04B17/345

CPC classification number: H04B17/345 ,  G01R31/2856 ,  G01R31/31709 ,  G01R31/31727 ,  G01R31/40 ,  H04B15/005 ,  H04B17/104

Abstract: Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.

公开(公告)号：US09998125B2

公开(公告)日：2018-06-12

申请号：US15025226

申请日：2013-11-19

Applicant: Intel Corporation

Inventor： Ganesh Balamurugan ,  Mozhgan Mansuri ,  Sami Hyvonen ,  Bryan K. Casper ,  Frank O'Mahony

IPC: H03L7/00 ,  G11C7/22 ,  H03K5/156 ,  H04L25/03 ,  H04B1/04 ,  G11C7/10

CPC classification number: H03L7/00 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/08 ,  H04B1/04 ,  H04L25/03

Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

公开(公告)号：US09935063B2

公开(公告)日：2018-04-03

申请号：US15201375

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Jihwan Kim ,  Ajay Balankutty ,  Anupriya Sriramulu ,  MD. Mohiuddin Mazumder ,  Frank O'Mahony ,  Zuoguo Wu ,  Kemal Aygun

IPC: H01L23/00 ,  H01L23/64 ,  H02H9/04 ,  H01L27/02 ,  H01L23/66

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.