公开(公告)号：US20190252102A1

公开(公告)日：2019-08-15

申请号：US15894418

申请日：2018-02-12

Applicant: INTEL CORPORATION

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01F1/20 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US10111338B2

公开(公告)日：2018-10-23

申请号：US15464123

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： Frank Truong ,  Dilan Seneviratne

IPC: H05K3/06 ,  H05K1/11 ,  H05K1/09 ,  H05K3/46

Abstract: Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.

公开(公告)号：US20180270953A1

公开(公告)日：2018-09-20

申请号：US15464123

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： Frank Truong ,  Dilan Seneviratne

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K3/06 ,  H05K1/09 ,  H05K1/111 ,  H05K1/116 ,  H05K3/061 ,  H05K3/068 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/032

Abstract: Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.

公开(公告)号：US11688692B2

公开(公告)日：2023-06-27

申请号：US17540079

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US11571876B2

公开(公告)日：2023-02-07

申请号：US16480593

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Praneeth Akkinepally ,  Frank Truong ,  Dilan Seneviratne

IPC: B32B27/36 ,  B32B7/12 ,  B32B15/20 ,  C09J7/29 ,  C09J7/40 ,  C09J11/00 ,  C08K5/17 ,  C08K5/37 ,  C09J7/25

Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.

公开(公告)号：US11348865B2

公开(公告)日：2022-05-31

申请号：US16587963

申请日：2019-09-30

Applicant: Intel Corporation

Inventor： Praneeth Akkinepally ,  Jieying Kong ,  Frank Truong

IPC: H01L23/498

Abstract: A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.

公开(公告)号：US11296186B2

公开(公告)日：2022-04-05

申请号：US16737680

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC: H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20200253037A1

公开(公告)日：2020-08-06

申请号：US16268813

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H05K1/11 ,  H01L23/498

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

公开(公告)号：US10068776B1

公开(公告)日：2018-09-04

申请号：US15637969

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Frank Truong ,  Praneeth Akkinepally ,  Shruti R. Jaywant ,  Dilan Seneviratne

IPC: H01L21/3105 ,  H01L21/312 ,  H01L21/4757 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/31053 ,  H01L21/02354 ,  H01L21/31058 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76885 ,  H01L22/12 ,  H01L22/30 ,  H01L23/498 ,  H01L23/5283

Abstract: An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal light beam. The planar surface encompasses a filled via that is in electrical and physical contact with a bond pad that is also on the planar surface.

公开(公告)号：US11855125B2

公开(公告)日：2023-12-26

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Brandon C. Marin ,  Jeremy Ecton ,  Hiroki Tanaka ,  Frank Truong

IPC: H01L21/48 ,  H01G4/008 ,  H01G4/28 ,  H01G4/12 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/28 ,  H01L21/4846

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.