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    HEAT SPREADING LAYER INTEGRATED WITHIN A COMPOSITE IC DIE STRUCTURE AND METHODS OF FORMING THE SAME
    16.
    发明申请
    HEAT SPREADING LAYER INTEGRATED WITHIN A COMPOSITE IC DIE STRUCTURE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210202347A1

    公开(公告)日：2021-07-01

    申请号：US16727703

    申请日：2019-12-26

    Applicant: Intel Corporation

    Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

    IPC: H01L23/373 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768

    Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

    MIXED HYBRID BONDING STRUCTURES AND METHODS OF FORMING THE SAME
    17.
    发明申请
    MIXED HYBRID BONDING STRUCTURES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210098411A1

    公开(公告)日：2021-04-01

    申请号：US16584522

    申请日：2019-09-26

    Applicant: Intel Corporation

    Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

    MULTI-USE PACKAGE ARCHITECTURE
    18.
    发明申请
    MULTI-USE PACKAGE ARCHITECTURE 审中-公开

    公开(公告)号：US20190287872A1

    公开(公告)日：2019-09-19

    申请号：US15925429

    申请日：2018-03-19

    Applicant: INTEL CORPORATION

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

    IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

    Electronic device package
    19.
    发明授权
    Electronic device package 有权

    公开(公告)号：US10249515B2

    公开(公告)日：2019-04-02

    申请号：US15089136

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Jimin Yao ,  Eric Li ,  Shawna Liff

    IPC: H01L21/56 ,  H01L23/31 ,  H01L21/60

    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.

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