公开(公告)号：US20190198436A1

公开(公告)日：2019-06-27

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01L23/49838 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F2027/2809 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US20190198228A1

公开(公告)日：2019-06-27

申请号：US15854460

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Lauren A. Link ,  Andrew J. Brown

IPC: H01F27/28 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01F27/2828 ,  H01L21/76802 ,  H01L23/5227 ,  H01L28/10

Abstract: An electronic structure may be fabricated comprising an electronic substrate having at least one photo-imageable dielectric layer and an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer. The electronic structure may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US11881463B2

公开(公告)日：2024-01-23

申请号：US17524375

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L25/00 ,  H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US20220230951A1

公开(公告)日：2022-07-21

申请号：US17715380

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01L25/16

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US20220068847A1

公开(公告)日：2022-03-03

申请号：US17524375

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US20220013265A1

公开(公告)日：2022-01-13

申请号：US17482855

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01F1/20 ,  H01L23/498 ,  H01L21/48 ,  H01F41/02 ,  H05K1/18 ,  H01F1/37 ,  H01F1/28

Abstract: An inductor may be fabricated comprising a magnetic material layer and an electrically conductive via or trace extending through the magnetic material layer, wherein the magnetic material layer comprises dielectric magnetic filler particles within a carrier material. Further embodiments may include incorporating the inductor of the present description into an electronic substrate and may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US20210050306A1

公开(公告)日：2021-02-18

申请号：US16541734

申请日：2019-08-15

Applicant: INTEL CORPORATION

Inventor： Lauren A. Link ,  Andrew J. Brown ,  Sheng C. Li ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

公开(公告)号：US11862552B2

公开(公告)日：2024-01-02

申请号：US17567639

申请日：2022-01-03

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F41/046 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/19 ,  H01L24/20 ,  H05K1/00 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US11610706B2

公开(公告)日：2023-03-21

申请号：US15870302

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Rahul Jain ,  Kyu Oh Lee ,  Sheng C. Li ,  Andrew J. Brown ,  Lauren A. Link

IPC: H01F1/42 ,  H01F27/38 ,  B32B27/38 ,  C22C45/04 ,  H01F17/00 ,  H01L23/498 ,  H01F27/28 ,  H01L21/56 ,  H01F17/06

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

公开(公告)号：US11251113B2

公开(公告)日：2022-02-15

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L21/48 ,  H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.