公开(公告)号：US09213666B2

公开(公告)日：2015-12-15

申请号：US14497567

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Eran Tamari ,  Mikal C. Hunsaker ,  Sridhar Lakshmanamurthy ,  Michael T. Klinglesmith ,  Blaise Fanning

IPC: G06F13/14 ,  G06F13/42 ,  G06F13/366 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/4036

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

公开(公告)号：US09075929B2

公开(公告)日：2015-07-07

申请号：US14578720

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/42 ,  G06F13/368

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

公开(公告)号：US11086812B2

公开(公告)日：2021-08-10

申请号：US14998222

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Shaun M. Conrad ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F13/42 ,  G06F13/362 ,  G06F13/40

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

公开(公告)号：US11016549B2

公开(公告)日：2021-05-25

申请号：US15870629

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Poh Thiam Teoh ,  Mikal C. Hunsaker ,  Su Wei Lim ,  Gim Chong Lee ,  Hooi Kar Loo ,  Shashitheren Kerisnan ,  Siang Lin Tan ,  Ming Chew Lee ,  Ngeok Kuan Wai ,  Li Len Lim

IPC: G06F1/26 ,  G06F1/10 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

公开(公告)号：US10157160B2

公开(公告)日：2018-12-18

申请号：US14865005

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Michael T. Klinglesmith ,  Mikal C. Hunsaker ,  William Knolla ,  Hartej Singh

IPC: G06F13/00 ,  G06F13/14 ,  G06F3/00 ,  G06F13/42 ,  G06F13/20 ,  G06F13/40

Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

公开(公告)号：US09064051B2

公开(公告)日：2015-06-23

申请号：US14295810

申请日：2014-06-04

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/366 ,  G06F15/78 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求 源代理程序在第一个时钟周期。 然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。 描述和要求保护其他实施例。

公开(公告)号：US20150113189A1

公开(公告)日：2015-04-23

申请号：US14578720

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F13/42 ,  G06F13/368

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求 源代理程序在第一个时钟周期。 然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。 描述和要求保护其他实施例。

公开(公告)号：US09921987B2

公开(公告)日：2018-03-20

申请号：US15218727

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16 ,  G11C29/52

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

公开(公告)号：US09753875B2

公开(公告)日：2017-09-05

申请号：US15001330

申请日：2016-01-20

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Mohan K. Nair ,  Joseph Murray ,  Rohit R. Verma ,  Gary J. Lavelle ,  Robert P. Adler

IPC: G06F13/364 ,  H04L12/28 ,  H04L12/54 ,  H04L12/701 ,  H04L12/761 ,  G06F15/78 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/385 ,  G06F13/4265 ,  G06F15/7807 ,  G06F15/7825 ,  G06F2213/0038 ,  H04L12/28 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US20170185559A1

公开(公告)日：2017-06-29

申请号：US14998222

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Shaun M. Conrad ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/4068

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.