公开(公告)号：US20200312793A1

公开(公告)日：2020-10-01

申请号：US16369708

申请日：2019-03-29

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D. Ecton

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

摘要： A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US10546916B2

公开(公告)日：2020-01-28

申请号：US16024223

申请日：2018-06-29

申请人： Intel Corporation

发明人： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC分类号： H01L29/00 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

摘要： Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20200006468A1

公开(公告)日：2020-01-02

申请号：US16024223

申请日：2018-06-29

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC分类号： H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

摘要： Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20190333861A1

公开(公告)日：2019-10-31

申请号：US16474019

申请日：2017-03-29

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manapalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

摘要： Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US11571876B2

公开(公告)日：2023-02-07

申请号：US16480593

申请日：2017-03-17

申请人： Intel Corporation

发明人： Praneeth Akkinepally ,  Frank Truong ,  Dilan Seneviratne

IPC分类号： B32B27/36 ,  B32B7/12 ,  B32B15/20 ,  C09J7/29 ,  C09J7/40 ,  C09J11/00 ,  C08K5/17 ,  C08K5/37 ,  C09J7/25

摘要： Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.

公开(公告)号：US11348865B2

公开(公告)日：2022-05-31

申请号：US16587963

申请日：2019-09-30

申请人： Intel Corporation

发明人： Praneeth Akkinepally ,  Jieying Kong ,  Frank Truong

IPC分类号： H01L23/498

摘要： A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.

公开(公告)号：US11296186B2

公开(公告)日：2022-04-05

申请号：US16737680

申请日：2020-01-08

申请人： Intel Corporation

发明人： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC分类号： H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00

摘要： Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20210366835A1

公开(公告)日：2021-11-25

申请号：US17391905

申请日：2021-08-02

申请人： Intel Corporation

发明人： Srinivas Venkata Ramanuja Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

摘要： Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated. substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US20210151393A1

公开(公告)日：2021-05-20

申请号：US17158634

申请日：2021-01-26

申请人： Intel Corporation

发明人： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

摘要： A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20180350709A1

公开(公告)日：2018-12-06

申请号：US15778042

申请日：2015-11-24

申请人： INTEL CORPORATION

发明人： Pramod Malatkar ,  Kyle Yazzie ,  Naga Sivakumar Yagnamurthy ,  Richard J. Harries ,  Dilan Seneviratne ,  Praneeth Akkinepally ,  Xuefei Wan ,  Yonggang Li ,  Robert L. Sankman

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L23/34 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49582 ,  H01L23/49816 ,  H01L23/562 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.