公开(公告)号：US10278318B2

公开(公告)日：2019-04-30

申请号：US14974113

申请日：2015-12-18

申请人： Intel Corporation

发明人： Kyle Yazzie ,  Pramod Malatkar ,  Xiao Lu ,  Daniel Chavez-Clemente

IPC分类号： H05K13/04 ,  H05K3/30

摘要： A method of assembly comprising providing an assembly probe, the assembly probe having an end coupling face; providing a droplet of fluid on the end coupling face of the assembly probe; coupling an electronic component to the end coupling face of the assembly probe with the fluid droplet, the electronic component having a peripheral dimension equal to or less than 2 mm in each of length, width and height; placing the electronic component on a substrate with the assembly probe; decoupling the electronic component from the end coupling face of the assembly probe; and assembling the electronic component to the substrate.

公开(公告)号：US20170176516A1

公开(公告)日：2017-06-22

申请号：US14976881

申请日：2015-12-21

申请人： INTEL CORPORATION

发明人： Mohit Mamodia ,  Kyle Yazzie ,  Dingying David Xu ,  Kuang Liu ,  Paul J. Diglio ,  Pramod Malatkar

IPC分类号： G01R31/28 ,  H05B3/26

CPC分类号： H05B3/267 ,  G01R31/2867 ,  G01R31/2875

摘要： A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

公开(公告)号：US20160276317A1

公开(公告)日：2016-09-22

申请号：US15170833

申请日：2016-06-01

申请人： Intel Corporation

发明人： Pramod Malatkar

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/83 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/538 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/80001 ,  H01L2224/83951 ,  H01L2224/92224 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00

摘要： The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

摘要翻译： 本公开涉及集成电路封装设计的领域，更具体地，涉及使用无凸起的构建层（BBUL）设计的封装。 本发明的实施例涉及制造微电子封装的领域，其中具有通硅通孔的第一微电子器件可以与第二微电子器件堆叠并且用于无扰性积聚层封装中。

公开(公告)号：US11201128B2

公开(公告)日：2021-12-14

申请号：US14998093

申请日：2015-12-23

申请人： Intel Corporation

发明人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

IPC分类号： H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

公开(公告)号：US20180350709A1

公开(公告)日：2018-12-06

申请号：US15778042

申请日：2015-11-24

申请人： INTEL CORPORATION

发明人： Pramod Malatkar ,  Kyle Yazzie ,  Naga Sivakumar Yagnamurthy ,  Richard J. Harries ,  Dilan Seneviratne ,  Praneeth Akkinepally ,  Xuefei Wan ,  Yonggang Li ,  Robert L. Sankman

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L23/34 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49582 ,  H01L23/49816 ,  H01L23/562 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.

公开(公告)号：US09831213B2

公开(公告)日：2017-11-28

申请号：US15170833

申请日：2016-06-01

申请人： Intel Corporation

发明人： Pramod Malatkar

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/11 ,  H01L25/07 ,  H01L41/083 ,  H01L25/065 ,  H01L23/522 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/83 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/538 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/80001 ,  H01L2224/83951 ,  H01L2224/92224 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00

摘要： The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

公开(公告)号：US09793225B2

公开(公告)日：2017-10-17

申请号：US15204303

申请日：2016-07-07

申请人： Intel Corporation

发明人： Pramod Malatkar ,  Richard J. Harries

IPC分类号： H05K7/00 ,  H01L23/00 ,  H05K1/02 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/485 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H05K1/0271

摘要： The present description relates to the field of fabricating microelectronic packages, wherein a microelectronic device may be attached to a microelectronic substrate with a compensator to control package warpage. The warpage compensator may be a low coefficient of thermal expansion material, including but not limited to silicon or a ceramic material, which is positioned on a land-side of the microelectronic device to counteract the thermal expansion effects of the microelectronic device.

公开(公告)号：US10231338B2

公开(公告)日：2019-03-12

申请号：US14748496

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： Naga Sivakumar Yagnamurthy ,  Huiyang Fei ,  Pramod Malatkar ,  Prasanna Raghavan ,  Robert Nickerson

IPC分类号： H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  B29C70/84 ,  B29C70/70 ,  B29C70/88 ,  B29C37/00 ,  B29C33/00 ,  B29C69/00 ,  G11C11/401 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  B29K63/00 ,  B29L31/34 ,  G11C5/04 ,  H05K1/14

摘要： Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.

公开(公告)号：US10090259B2

公开(公告)日：2018-10-02

申请号：US14757835

申请日：2015-12-26

申请人： Intel Corporation

发明人： Pramod Malatkar ,  Sairam Agraharam ,  Shawna Liff

IPC分类号： H01L23/04 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L23/13 ,  H01L21/02 ,  H01L29/06 ,  H05K1/02

摘要： Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. An electronic device die is also provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. In addition, an electronic device package is provided that can comprise a substrate having a top surface configured to receive a die and a bottom surface opposing the top surface. The package can also include a die having a top surface and a bottom surface opposing the top surface. The die can be coupled to the top surface of the substrate. The top surface and/or the bottom surface of either the substrate, or the die, or both can have a non-rectangular shaped perimeter.

公开(公告)号：US20180089984A1

公开(公告)日：2018-03-29

申请号：US15277811

申请日：2016-09-27

申请人： Intel Corporation

发明人： Vijay Krishnan Subramanian ,  Steven A. Klein ,  Pramod Malatkar ,  Rajendra C. Dias ,  Aleksandar Aleksov ,  Jason P. Glumbik ,  Nadine L. Dabby

IPC分类号： G08B21/18 ,  H05K1/02 ,  H05K1/18 ,  G01R31/28

CPC分类号： G01R31/2846 ,  H05K1/0268 ,  H05K1/189 ,  H05K2201/09263 ,  H05K2201/10151

摘要： Techniques and mechanisms for determining a level of degradation of flexible circuitry. In an embodiment, a flexible substrate has disposed therein first circuitry and one or more components coupled thereto, the one or more components to monitor a physical property of the first circuitry. Further disposed in or on the flexible substrate are memory resources to store predefined reference information which corresponds amounts of the physical property each with a different respective level of degradation. Evaluation logic accesses the reference information to determine, based on a detected amount of the physical property, a level of degradation of second circuitry. In another embodiment, the second circuitry is more flexible, as compared to the first circuitry.