公开(公告)号：US10296238B2

公开(公告)日：2019-05-21

申请号：US14975160

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US10048877B2

公开(公告)日：2018-08-14

申请号：US14976921

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Shaun M. Miller ,  Richard P. Mangold

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/20

Abstract: Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.

公开(公告)号：US09934859B1

公开(公告)日：2018-04-03

申请号：US15391763

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Prashant S. Damle ,  Kunal A. Khochare ,  Philip Hillier ,  Jeffrey W. Ryden ,  Richard P. Mangold

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028

Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.

公开(公告)号：US20170068537A1

公开(公告)日：2017-03-09

申请号：US14845503

申请日：2015-09-04

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Camille C. Raad ,  Richard P. Mangold ,  Theodros Yigzaw

IPC: G06F9/30 ,  G06F11/30 ,  G06F11/16 ,  G11C29/44 ,  G06F11/07

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1612 ,  G06F11/167 ,  G06F12/00 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

Abstract: Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.

Abstract translation: 如果存储在存储器区域中的易失性数据不对应于已知的数据模式，则系统和方法可以提供用于检测在存储器区域处于中毒状态时读取操作被引导到存储器区域并清除中毒状态。 此外，如果存储在存储器区域中的易失性数据对应于已知数据模式，则存储器区域可以被维持在中毒状态。 在一个示例中，可以检测到错误，其中错误与针对存储器区域的写入操作相关联。 在这种情况下，响应于错误可以为易失性数据设置中毒状态，并且可以将已知数据模式写入存储器区域。

公开(公告)号：US09477409B2

公开(公告)日：2016-10-25

申请号：US14318573

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajesh M. Sankaran ,  Murugasamy K. Nachimuthu ,  Richard P. Mangold

IPC: G06F3/06 ,  G11C7/20

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0679 ,  G06F8/71 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4416 ,  G06F11/1417 ,  G06F11/3476 ,  G11C7/20

Abstract: Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了基于非易失性存储器（NVM）技术来加速引导时间归零的存储器的方法和装置。 在一个实施例中，存储设备存储对应于非易失性存储器的一部分的引导版本号。 存储器控制器逻辑导致响应于每个后续引导事件的存储的引导版本号的更新。 存储器控制器逻辑响应于针对非易失性存储器的部分的读操作和存储的引导版本号与当前引导版本号之间的不匹配而返回零。 还公开并要求保护其他实施例。

公开(公告)号：US10296250B2

公开(公告)日：2019-05-21

申请号：US15176650

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Benjamin L. Walker ,  August A. Camber ,  Jonathan Bryan Stern ,  Sanjeev Trika ,  Richard P. Mangold ,  Jawad Basit Khan ,  Anand Ramalingam

IPC: G06F17/30 ,  G06F3/06 ,  G06F12/06

Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.

公开(公告)号：US20190102320A1

公开(公告)日：2019-04-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US10248343B2

公开(公告)日：2019-04-02

申请号：US15357783

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Jason B. Akers ,  Knut S. Grimsrud ,  Robert J. Royer, Jr. ,  Richard P. Mangold ,  Sanjeev N. Trika

IPC: G11C14/00 ,  G06F3/06 ,  G11C5/14 ,  G06F1/3287 ,  G11C7/10 ,  G06F11/14

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

公开(公告)号：US20170062023A1

公开(公告)日：2017-03-02

申请号：US14836923

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Shamanna M. Datta ,  Richard P. Mangold ,  Mahesh S. Natu

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G06F2212/72 ,  G06F2212/7209 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/4401 ,  G11C29/70

Abstract: Apparatus, systems, and methods to implement boot operations in nonvolatile storage devices can include, in one example, a controller comprising logic to receive a power down instruction, record a timestamp associated with the power down instruction, and store the timestamp in a nonvolatile memory table communicatively coupled to the controller. Other examples are also disclosed and claimed.

Abstract translation: 在一个示例中，可以包括用于实现非易失性存储设备中的引导操作的装置，系统和方法，所述控制器包括用于接收掉电指令，记录与掉电指令相关联的时间戳并将所述时间戳存储在非易失性存储器 表通信耦合到控制器。 还公开并要求保护其他实例。

公开(公告)号：US20160378352A1

公开(公告)日：2016-12-29

申请号：US14751450

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard P. Mangold ,  Vinodh Gopal ,  Rowel S. Garcia ,  Knut S. Grimsrud

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7203 ,  G06F2212/7205

Abstract: Methods and apparatus related to efficient Solid State Drive (SSD) data compression scheme and layout are described. In one embodiment, logic, coupled to non-volatile memory, receives data (e.g., from a host) and compresses the data to generate compressed data prior to storage of the compressed data in the non-volatile memory. The compressed data includes a compressed version of the data, size of the compressed data, common meta information, and final meta information. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与高效固态硬盘（SSD）数据压缩方案和布局相关的方法和设备。 在一个实施例中，耦合到非易失性存储器的逻辑从存储压缩数据到非易失性存储器之前接收数据（例如来自主机）并压缩数据以生成压缩数据。 压缩数据包括数据的压缩版本，压缩数据的大小，公共元信息和最终元信息。 还公开并要求保护其他实施例。