公开(公告)号：US20180358467A1

公开(公告)日：2018-12-13

申请号：US16108610

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  B82Y40/00

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

公开(公告)号：US20180158737A1

公开(公告)日：2018-06-07

申请号：US15576248

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Karthik JAMBUNATHAN

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.

公开(公告)号：US20170053998A1

公开(公告)日：2017-02-23

申请号：US15118838

申请日：2014-03-24

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Daniel A. SIMON ,  Kelin J. KUHN ,  Curtis W. WARD

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.

Abstract translation: 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，通过在与沟道区相邻蚀刻的凹坑中沉积光可定义的间隔物材料来形成内部间隔物。 通过改变凹坑之外的材料的蚀刻特性并且选择性地去除在凹坑之外的改变的光可定义材料，可光限定的材料保留在凹坑中。

公开(公告)号：US20160211322A1

公开(公告)日：2016-07-21

申请号：US14916093

申请日：2013-10-03

Applicant: INTEL CORPORATION

Inventor： Seiyon KIM ,  Daniel A. SIMON ,  Nadia M. RAHHAL-ORABI ,  Chul-Hyun LIM ,  Kelin J. KUHN

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract translation: 本描述的纳米线晶体管可以在其制造期间使用牺牲间隔物形成的内部间隔物来制造。 一旦形成了纳米线晶体管，就可以去除位于晶体管栅极和源极之间的排列（分别）的牺牲间隔物。 然后可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并且可以沉积介电材料以填充沟道纳米线之间的空间。 可以除去不在通道纳米线之间的电介质材料以形成内部间隔物。 位于晶体管栅极和源极之间的位置（分别）的外部间隔物可以随后形成在内部间隔物和晶体管沟道纳米线附近。

公开(公告)号：US20230046755A1

公开(公告)日：2023-02-16

申请号：US17978038

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20210043755A1

公开(公告)日：2021-02-11

申请号：US17080458

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L29/778

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20210036137A1

公开(公告)日：2021-02-04

申请号：US17072992

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Cory E. WEBER ,  Patrick H. KEYS ,  Seiyon KIM ,  Michael G. HAVERTY ,  Sadasivan SHANKAR

IPC: H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

公开(公告)号：US20190252525A1

公开(公告)日：2019-08-15

申请号：US16396088

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7782 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20190058053A1

公开(公告)日：2019-02-21

申请号：US15770628

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Seiyon KIM ,  Benjamin CHU-KUNG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66583 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/267 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

公开(公告)号：US20180122901A1

公开(公告)日：2018-05-03

申请号：US15859226

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.