公开(公告)号：US10665222B2

公开(公告)日：2020-05-26

申请号：US16022376

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Muhammad Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Wootaek Lim ,  Tobias Bocklet ,  David Pearce

IPC: G01L15/00 ,  G10L15/02 ,  G10L25/03 ,  G10L15/20 ,  G10L25/24 ,  G10L25/18 ,  G10L25/09

Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.

公开(公告)号：US20190190725A1

公开(公告)日：2019-06-20

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

CPC classification number: H04L9/3278

Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US20190094931A1

公开(公告)日：2019-03-28

申请号：US15718991

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Khondker Z. Ahmed ,  Vivek K. De ,  Nachiket V. Desai ,  Suhwan Kim ,  Harish K. Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram R. Vangal

IPC: G06F1/26 ,  G06N99/00

Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.

公开(公告)号：US20190094897A1

公开(公告)日：2019-03-28

申请号：US15712813

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Turbo Majumder ,  Vivek De

IPC: G05F1/66 ,  G05F1/46 ,  G06F1/32

Abstract: Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.

公开(公告)号：US20190006939A1

公开(公告)日：2019-01-03

申请号：US15638643

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Harish Krishnamurthy ,  Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M1/42 ,  H04W84/20

Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

公开(公告)号：US20240111826A1

公开(公告)日：2024-04-04

申请号：US17937252

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Kevin Hurd ,  Changwon Rhee ,  Jorge Parra ,  Fangwen Fu ,  Theo Drane ,  William Zorn ,  Peter Caday ,  Gregory Henry ,  Guei-Yuan Lueh ,  Farzad Chehrazi ,  Amit Karande ,  Turbo Majumder ,  Xinmin Tian ,  Milind Girkar ,  Hong Jiang

IPC: G06F17/16 ,  G06F7/544 ,  G06T1/20

CPC classification number: G06F17/16 ,  G06F7/5443 ,  G06T1/20

Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.

公开(公告)号：US20220308833A1

公开(公告)日：2022-09-29

申请号：US17211188

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Turbo Majumder ,  Kamal Sinha ,  Altug Koker

IPC: G06F7/523 ,  G06F1/03

Abstract: An apparatus to facilitate a multiplication circuit based on constituent partial product lookup table is disclosed. The apparatus includes a systolic array to receive first source data and second source data; while the first source data is constant and for each of a plurality of subsets of the second source data: determine whether a pre-computed partial product for the first source data and a subset of the plurality of subsets is stored in a lookup table; responsive to the pre-computed partial product being stored in the lookup table, use the pre-computed partial product as a partial product for the first source data and the subset; and responsive to the pre-computed partial product being absent from the lookup table: compute the partial product for the first source data and the subset; and store the partial product as the pre-computed partial product in the lookup table.

公开(公告)号：US20210193196A1

公开(公告)日：2021-06-24

申请号：US16725747

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Turbo Majumder ,  Iqbal Rajwani ,  Andrew Lines ,  Altug Koker ,  Lakshminarayanan Striramassarma ,  Muhammad Khellah

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

公开(公告)号：US10958079B2

公开(公告)日：2021-03-23

申请号：US15939120

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Khondker Z. Ahmed ,  Vivek K. De ,  Nachiket V. Desai ,  Suhwan Kim ,  Harish K. Krishnamurthy ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav A. Vaidya ,  Sriram R. Vangal

IPC: H02J1/00 ,  H02J3/00 ,  H02J3/38 ,  H02M3/156 ,  G05F1/67 ,  H02M1/10 ,  H02M3/07 ,  H02M1/00

Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.

公开(公告)号：US20200005468A1

公开(公告)日：2020-01-02

申请号：US16565304

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Turbo Majumder ,  Mohamed Elmalaki ,  Muhammad Khellah ,  Charles Augustine

IPC: G06T7/215 ,  G06K9/00

Abstract: Methods, systems, and articles herein are directed to event-driven object segmentation to track events rather than tracking all pixel locations in an image.