公开(公告)号：US20160351498A1

公开(公告)日：2016-12-01

申请号：US15117621

申请日：2014-03-24

Applicant: INTEL CORPORATION

Inventor： TING CHANG ,  CHIA-HONG JAN ,  WALID M. HAFEZ

IPC: H01L23/525 ,  H01L27/112 ,  G11C17/16

CPC classification number: H01L23/5252 ,  G11C11/005 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

Abstract translation: 公开了用于有效实现包括非易失性和易失性存储器的可编程存储器阵列电路架构的技术和电路。 存储器电路采用包括1T位单元的阵列的反熔断器方案，其中每个位单元有效地包含一个栅极或类似晶体管的器件，其为该位单元提供反熔丝元件和选择器器件。 特别地，位单元器件具有不对称的基于沟槽的源极/漏极触点，使得一个触点与间隔物和栅极金属结合形成电容器，而另一个触点与掺杂扩散区域和栅极金属结合形成二极管。 电容器用作位单元的反熔断元件，并且可以通过分解间隔件来编程。 该二极管有效地提供肖特基结，其作为选择器装置，其可以消除共享相同位线/字线的位单元的程序和读取干扰。

公开(公告)号：US20160211369A1

公开(公告)日：2016-07-21

申请号：US14913326

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： CHIA-HONG JAN ,  WALID M. HAFEZ ,  CURTIS TSAI ,  JENG-YA D. YEH ,  JOODONG PARK

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。

公开(公告)号：US20200219772A1

公开(公告)日：2020-07-09

申请号：US16239059

申请日：2019-01-03

Applicant: INTEL CORPORATION

Inventor： RAHUL RAMASWAMY ,  NIDHI NIDHI ,  WALID M. HAFEZ ,  JOHANN C. RODE ,  PAUL FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANSAPTAK DASGUPTA

IPC: H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/872 ,  H01L29/66

Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).

公开(公告)号：US20190027604A1

公开(公告)日：2019-01-24

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： CHEN-GUAN LEE ,  WALID M. HAFEZ ,  JOODONG PARK ,  CHIA-HONG JAN ,  HSU-YU CHANG

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

公开(公告)号：US20170155004A1

公开(公告)日：2017-06-01

申请号：US15127207

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： KINYIP PHOA ,  NIDHI NIDHI ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  YI WEI CHEN

IPC: H01L31/0224 ,  H02S40/38 ,  H01L31/18 ,  H01L31/028 ,  H01L31/05 ,  H01L31/056 ,  H01L31/068

CPC classification number: H01L31/022458 ,  H01L31/022475 ,  H01L31/028 ,  H01L31/047 ,  H01L31/0516 ,  H01L31/056 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/1884 ,  H02S40/38 ,  Y02E10/52 ,  Y02E10/547

Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.

公开(公告)号：US20170069725A1

公开(公告)日：2017-03-09

申请号：US15122796

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： GOPINATH BHIMARASETTI ,  WALID M. HAFEZ ,  JOODONG PARK ,  WEIMIN HAN ,  RAYMOND E. COTNER ,  CHIA-HONG JAN

IPC: H01L29/36 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/36 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7853

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract translation: 描述了具有掺杂子鳍区域的ω鳍片的非平面半导体器件以及制造具有掺杂子鳍片区域的具有Ω形翅片的非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底上方的多个半导体鳍片，每个半导体鳍片具有在突出部分下方的副鳍片部分，子鳍片部分比突出部分窄。 固态掺杂剂源层设置在半导体衬底之上，与子鳍区域共形而不是多个半导体鳍片中的每一个的突出部分。 隔离层设置在固态掺杂剂源层上方和多个半导体鳍片的子鳍片区域之间。 栅极叠层设置在隔离层上方并与多个半导体鳍片中的每一个的突起部分保形。

公开(公告)号：US20160225671A1

公开(公告)日：2016-08-04

申请号：US14914179

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： ROMAN W. OLAC-VAW ,  WALID M. HAFEZ ,  CHIA-HONG JAN ,  PEI-CHI LIU

IPC: H01L21/8234 ,  H01L23/528 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract translation: 描述了在公共基板上具有不同功函数的非平面I / O和逻辑半导体器件以及在公共基板上制造具有不同功函数的非平面I / O和逻辑半导体器件的方法。 例如，半导体结构包括设置在基板上方的第一半导体器件。 第一半导体器件具有导电类型，并且包括具有第一功函数的栅电极。 半导体结构还包括设置在基板上方的第二半导体器件。 第二半导体器件具有导电类型，并且包括具有第二不同功函数的栅电极。

公开(公告)号：US20160035735A1

公开(公告)日：2016-02-04

申请号：US14880814

申请日：2015-10-12

Applicant: INTEL CORPORATION

Inventor： WALID M. HAFEZ ,  CHIA-HONG JAN ,  CURTIS TSAI ,  JOODONG PARK ,  JENG-YA D. YEH

IPC: H01L27/112

CPC classification number: H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

Abstract translation: 本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。 在一些实施例中，反熔丝存储器元件被配置为非平面拓扑，例如FinFET拓扑。 在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。 在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。 翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％ 。