公开(公告)号：US10978399B2

公开(公告)日：2021-04-13

申请号：US16474589

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Sai Boyapati ,  Wei-Lun Kane Jen ,  Javier Soto Gonzalez

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01L23/495 ,  H01L23/532

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.

公开(公告)号：US20200221577A1

公开(公告)日：2020-07-09

申请号：US16819899

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Amruthavalli Palavi Alur ,  Wei-Lun Kane Jen ,  Sriram Srinivasan

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11

Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

公开(公告)号：US10672713B2

公开(公告)日：2020-06-02

申请号：US16135695

申请日：2018-09-19

Applicant: Intel Corporation

Inventor： Mihir K Roy ,  Stefanie M Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/13 ,  H05K1/14 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K3/46 ,  H01L23/00 ,  H05K1/18 ,  H05K3/34

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US20190355642A1

公开(公告)日：2019-11-21

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/367 ,  H01L23/538 ,  H01L21/56

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US09496209B2

公开(公告)日：2016-11-15

申请号：US14992535

申请日：2016-01-11

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/14 ,  H01L23/538 ,  H01L21/48 ,  H05K1/03 ,  H05K1/14 ,  H05K3/46 ,  H01L23/00 ,  H05K1/18

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US20240321762A1

公开(公告)日：2024-09-26

申请号：US18678813

申请日：2024-05-30

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H05K1/141 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US12002762B2

公开(公告)日：2024-06-04

申请号：US16889190

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Mihir K Roy ,  Stefanie M Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14 ,  H05K1/03 ,  H05K1/18 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H05K1/141 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US11508662B2

公开(公告)日：2022-11-22

申请号：US16322423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US10980129B2

公开(公告)日：2021-04-13

申请号：US16819899

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Amruthavalli Pallavi Alur ,  Wei-Lun Kane Jen ,  Sriram Srinivasan

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/30 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

公开(公告)号：US20200294924A1

公开(公告)日：2020-09-17

申请号：US16889190

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/13 ,  H05K1/14 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.