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    Technique for fabrication of microelectronic capacitors and resistors
    13.
    发明授权
    Technique for fabrication of microelectronic capacitors and resistors 有权
    微电子电容器和电阻器制造技术

    公开(公告)号：US09385177B2

    公开(公告)日：2016-07-05

    申请号：US14068198

    申请日：2013-10-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

    IPC: H01L49/02 ,  H01L23/525 ,  H01L27/01 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/321

    CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

    Abstract translation: 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 制造这种结构的方法巧妙地利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些基础形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

    INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS
    14.
    发明申请
    INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS 有权
    具有大型自对准VIAS的互连结构

    公开(公告)号：US20150279784A1

    公开(公告)日：2015-10-01

    申请号：US14231448

    申请日：2014-03-31

    Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

    Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Terry Spooner ,  Nicole A. Saulnier

    IPC: H01L23/532 ,  G03F1/36 ,  H01L21/768

    CPC classification number: G03F1/36 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

    Abstract translation: 公开了一种容纳小金属线和大通孔的波浪线互连结构。 用于图形金属线沟槽的光刻掩模设计使用光学邻近校正（OPC）技术来使用矩形不透明特征来近似波浪线。 可以使用自对准双镶嵌工艺形成大通孔，而不需要单独的通孔光刻掩模。 相反，牺牲层允许蚀刻下面的厚介质块，同时保护对应于金属线互连的沟槽的窄特征。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 通过提升通孔的收缩约束，从而允许通孔覆盖区超过金属线宽度的最小尺寸，为另外的工艺世代清除了一条路径，以继续将金属线收缩到低于10nm的尺寸。

    ELECTROSTATIC DISCHARGE DEVICES FOR INTEGRATED CIRCUITS
    17.
    发明申请
    ELECTROSTATIC DISCHARGE DEVICES FOR INTEGRATED CIRCUITS 有权
    用于集成电路的静电放电装置

    公开(公告)号：US20140175610A1

    公开(公告)日：2014-06-26

    申请号：US13725666

    申请日：2012-12-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

    Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

    IPC: H01L27/02 ,  H01L21/266

    CPC classification number: H01L27/0248 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/0255

    Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.

    Abstract translation: 可以制造用于保护集成电路免受静电放电的结二极管阵列，以包括各种尺寸的对称和/或非对称结二极管。 二极管可以配置为通过未封装的触点提供低电压和电流放电，或通过封装的触点提供高电压和电流放电。 在制造结二极管阵列中使用倾斜植入物允许使用单个硬掩模来植入多个离子物质。 此外，可以为每个种类以及其他参数（例如，植入能量，植入物掩模厚度和掩模开口的尺寸）选择不同的植入物倾斜角度，以便制造植入区域的形状。 如果需要，可以使用相同的植入物硬掩模，在已经形成的二极管之间插入隔离区域。 可以使用掩埋氧化物层来防止掺杂剂扩散到超过选定深度的衬底中。

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