公开(公告)号：US11158715B2

公开(公告)日：2021-10-26

申请号：US16447614

申请日：2019-06-20

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.

公开(公告)号：US11133309B2

公开(公告)日：2021-09-28

申请号：US16420753

申请日：2019-05-23

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

公开(公告)号：US11101182B2

公开(公告)日：2021-08-24

申请号：US16698052

申请日：2019-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L29/06 ,  H01L29/49 ,  B82Y10/00 ,  H01L21/3065

Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.

公开(公告)号：US20210233818A1

公开(公告)日：2021-07-29

申请号：US17232295

申请日：2021-04-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of forming the same include forming first recesses in a first stack of alternating sacrificial layers and channel layers. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers and the first inner spacer sub-layer are replaced with a gate stack in contact with the second inner spacer sub-layer.

公开(公告)号：US20210210634A1

公开(公告)日：2021-07-08

申请号：US16735946

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Alexander Reznicek ,  Xin Miao ,  Richard Glen Southwick, III

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/764 ,  H01L29/08 ,  H01L29/10

Abstract: A method of forming a vertical transport field-effect transistor (VFET) is provided. The method includes forming vertical fin channels by etching part way through a substrate. The method further includes forming a bottom source/drain electrode partially into the substrate and beneath the vertical fin channels. A gate dielectric layer is then formed on the vertical fin channels. A gate conductor layer is then formed on the gate dielectric layer. A height of the gate conductor layer is less than a height of the vertical fin channels. The method further includes forming a spacer layer on a top surface of the gate conductor layer. The method also includes forming a top source/drain electrode on a top surface of the vertical fin channels. A gap exists between the top source/drain electrode and the spacer layer.

公开(公告)号：US20210202749A1

公开(公告)日：2021-07-01

申请号：US16728462

申请日：2019-12-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Alexander Reznicek ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor structure including a nanosheet stack on a silicon germanium on insulator substrate, the nanosheet stack including alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another, a gate conductor orthogonal to the nanosheet stack and wrapping around the semiconductor channel material layers of the nanosheet stack, and a gate contact on the gate conductor layer adjacent to the nanosheet stack.

公开(公告)号：US11043598B2

公开(公告)日：2021-06-22

申请号：US16205344

申请日：2018-11-30

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

IPC: H01L29/786 ,  H01L29/10 ,  H01L21/324 ,  H01L29/40 ,  H01L29/417

Abstract: A method of forming a semiconductor structure includes forming a metal liner above and in direct contact with a bottom source/drain region, a fin spacer on sidewalls of a fin extending upward from a substrate and a hard mask positioned on top of the fin, the bottom source/drain region includes an epitaxially grown material in direct contact with a bottom portion of the fin not covered by the fin spacer, forming an organic planarization layer directly above the metal liner, simultaneously etching the organic planarization layer and the metal liner until all portions of the metal liner perpendicular to the substrate have been removed and only portions of the metal liner parallel to the substrate remain in contact with the bottom source/drain region, and annealing the semiconductor structure to form a metal silicide layer from the portions of the metal liner in contact with the bottom source/drain region.

公开(公告)号：US20210183710A1

公开(公告)日：2021-06-17

申请号：US17166692

申请日：2021-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Choonghyun Lee ,  Pouya Hashemi ,  Jingyun Zhang

IPC: H01L21/8238 ,  H01L29/51 ,  H01L21/28 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

公开(公告)号：US11024740B2

公开(公告)日：2021-06-01

申请号：US16420118

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Takashi Ando ,  Alexander Reznicek ,  Jingyun Zhang ,  Pouya Hashemi

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/12

Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.

公开(公告)号：US11018192B2

公开(公告)日：2021-05-25

申请号：US16741786

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments of the invention include resulting structures and a method for fabricating a vertical ReRAM array structure. The embodiments of the invention include forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, masking one or more portions of a topmost layer of the alternating layers, and etching one or more portions of the alternating layers down to the metal layer. Embodiments of the invention also include depositing a lateral electrode layer over the etched one or more portions of the alternating layers, performing an etch back on the lateral electrode layer, and forming a vertical electrode layer over the structures.