公开(公告)号：US09190419B2

公开(公告)日：2015-11-17

申请号：US13761430

申请日：2013-02-07

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/861 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/861

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层上形成氧化物层。 在SOI层和氧化物层中图案化至少一个第一组和至少一个第二组翅片。 在作为晶体管器件的沟道区域的第一组翅片的每一个的一部分上选择性地形成保形栅极电介质层。 第一金属栅极叠层形成在第一组散热片的每一个作为晶体管器件的沟道区域的部分上的保形栅极电介质层上。 在作为二极管装置的通道区域的第二组翅片的每一个的一部分上形成第二金属栅极堆叠。

公开(公告)号：US20150303303A1

公开(公告)日：2015-10-22

申请号：US14256225

申请日：2014-04-18

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/06 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

Abstract translation: 在基板的表面上形成包括硅锗合金部和硅部的散热片。 牺牲栅结构然后形成跨越每个鳍堆叠。 暴露的硅锗合金部分被氧化，而被牺牲栅极结构覆盖的硅锗合金部分不被氧化。 形成具有与每个牺牲栅极结构的最顶表面共面的最顶表面的电介质材料，然后去除每个牺牲栅极结构。 去除非氧化硅锗合金部分，悬浮在每个未氧化的硅锗合金部分上存在的硅部分。 然后在每个悬置的硅部分周围形成功能门结构。 氧化硅锗合金部分保留并向悬浮硅部分的通道部分提供应力。

公开(公告)号：US09059289B2

公开(公告)日：2015-06-16

申请号：US14023868

申请日：2013-09-11

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L21/77 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

公开(公告)号：US09058441B2

公开(公告)日：2015-06-16

申请号：US14317013

申请日：2014-06-27

Applicant: International Business Machines Corporation

Inventor： Wilfried Ernest-August Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Hailing Wang ,  Richard Q. Williams

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F17/5036

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个翅片。 该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件（IOFF），并且确定用于关断finFET器件（VOFF）的电压模型 ）。 该方法还包括将FinFET模型拟合到VOFF。

公开(公告)号：US08928083B2

公开(公告)日：2015-01-06

申请号：US13967888

申请日：2013-08-15

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/861

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

公开(公告)号：US20140264605A1

公开(公告)日：2014-09-18

申请号：US13961003

申请日：2013-08-07

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L23/48 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US20140217506A1

公开(公告)日：2014-08-07

申请号：US13761430

申请日：2013-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/861

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层上形成氧化物层。 在SOI层和氧化物层中图案化至少一个第一组和至少一个第二组翅片。 在作为晶体管器件的沟道区域的第一组翅片的每一个的一部分上选择性地形成保形栅极电介质层。 第一金属栅极叠层形成在第一组散热片的每一个作为晶体管器件的沟道区域的部分上的保形栅极电介质层上。 在作为二极管装置的通道区域的第二组翅片的每一个的一部分上形成第二金属栅极堆叠。

公开(公告)号：US08518770B2

公开(公告)日：2013-08-27

申请号：US13628169

申请日：2012-09-27

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Josephine B. Chang

IPC: H01L21/8238

CPC classification number: H01L29/66795 ,  H01L29/66636 ,  H01L29/785

Abstract: A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h1; reducing the height of the channel structure external to the gate structure so as to have a second height (h2); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.

Abstract translation: 一种制造晶体管的方法，包括在衬底上形成至少一个导电沟道结构，所述沟道具有长度，宽度和第一高度（h1）; 在所述衬底上形成栅极结构，所述栅极结构具有长度，宽度和高度，所述栅极结构垂直于所述沟道结构并且形成在所述沟道结构上，使得所述沟道结构穿过所述栅极结构的宽度 ，其中栅极结构的高度大于h1; 减小栅极结构外部的沟道结构的高度以便具有第二高度（h2）; 以及至少部分地在所述栅极结构外部的所述至少一个沟道结构上沉积硅化物层。

公开(公告)号：US20130171813A1

公开(公告)日：2013-07-04

申请号：US13775369

申请日：2013-02-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

IPC: H01L29/66

CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.

Abstract translation: 一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成 在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

公开(公告)号：US20130161745A1

公开(公告)日：2013-06-27

申请号：US13628225

申请日：2012-09-27

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78621

Abstract: In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described.

Abstract translation: 在一个实施例中，晶体管结构包括设置在半导体本体的表面上的栅极堆叠。 栅极堆叠具有围绕栅极金属的栅极电介质层，并且覆盖半导体主体中的沟道区域。 晶体管结构还包括具有源极延伸区域和漏极的源极，该漏极延伸区域形成在半导体本体中，其中每个延伸区域具有与栅极叠层的边缘重叠的尖锐的突变结。 还包括在源极和漏极之间的半导体本体中的通道下方具有注入的掺杂物质的穿孔停止区域。 还存在具有位于穿通止动区域和通道之间的注入的掺杂剂物质的浅沟道区域。 描述了体半导体和绝缘体上硅晶体管实施例。