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公开(公告)号：US11609817B2
公开(公告)日：2023-03-21
申请号：US17470100
申请日：2021-09-09
Applicant: International Business Machines Corporation
Inventor： Patrick James Meaney , Glenn David Gilda , David D. Cadigan , Lawrence Jones
IPC: G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , G06F11/10 , G06F11/07 , G06F12/0862 , G11C29/42 , G11C11/406 , G06F13/16
Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.
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公开(公告)号：US11200119B2
公开(公告)日：2021-12-14
申请号：US16741008
申请日：2020-01-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Patrick James Meaney , Glenn David Gilda , David D. Cadigan , Lawrence Jones
IPC: G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , G06F11/10 , G06F11/07 , G06F12/0862 , G11C29/42 , G11C11/406 , G06F13/16
Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.
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公开(公告)号：US20180365177A1
公开(公告)日：2018-12-20
申请号：US15623960
申请日：2017-06-15
Applicant: International Business Machines Corporation
Inventor： David D. Cadigan , Thomas J. Dewkett , Glenn D. Gilda , Patrick J. Meaney , Craig R. Walters
IPC: G06F13/16
CPC classification number: G06F13/1684 , G06F13/1647
Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.
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公开(公告)号：US20180308545A1
公开(公告)日：2018-10-25
申请号：US15810290
申请日：2017-11-13
Applicant: International Business Machines Corporation
Inventor： David D. Cadigan , William V. Huott , Adam J. McPadden , Anuwat Saetow
IPC: G11C13/00 , G11C14/00 , G11C29/12 , G11C11/419
CPC classification number: G11C13/0069 , G11C7/12 , G11C11/412 , G11C11/4125 , G11C11/413 , G11C11/419 , G11C13/0004 , G11C14/0081 , G11C14/009 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/50012 , G11C2029/1204
Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
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公开(公告)号：US20180308544A1
公开(公告)日：2018-10-25
申请号：US15496114
申请日：2017-04-25
Applicant: International Business Machines Corporation
Inventor： David D. Cadigan , William V. Huott , Adam J. McPadden , Anuwat Saetow
IPC: G11C13/00 , G11C11/419 , G11C29/12 , G11C14/00
CPC classification number: G11C13/0069 , G11C7/12 , G11C11/412 , G11C11/4125 , G11C11/413 , G11C11/419 , G11C13/0004 , G11C14/0081 , G11C14/009 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/50012 , G11C2029/1204
Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
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Patent Agency Ranking
公开(公告)号：US20170300338A1
公开(公告)日：2017-10-19
申请号：US15099047
申请日：2016-04-14
Applicant: International Business Machines Corporation
Inventor： David D. Cadigan , Stephen P. Glancy , William V. Huott , Kyu-hyoun Kim , Adam J. McPadden , Anuwat Saetow , Gary A. Tressler
CPC classification number: G06F9/4403 , G06F1/04
Abstract: A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.
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公开(公告)号：US09558850B1
公开(公告)日：2017-01-31
申请号：US14955183
申请日：2015-12-01
Applicant: International Business Machines Corporation
Inventor： John S. Bialas, Jr. , David D. Cadigan , Stephen P. Glancy , Warren E. Maule , Gary A. Van Huben
IPC: G11C29/50 , G11C11/401 , G11C11/4076
CPC classification number: G11C7/22 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C29/50012 , G11C2029/5004 , G11C2207/2254
Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.
Abstract translation: 用于高效数据眼睛训练的系统和方法减少了用于校准一个或多个存储器设备的时间和资源。 时间校准机制通过减少充分确定存储器件的数据眼的边界所需的数量测试来减少用于校准的时间和资源。 对于电压参考的一个或多个值，时间校准机制执行最少数量的测试以找到保持和建立时间的数据眼的边缘。
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公开(公告)号：US10897239B1
公开(公告)日：2021-01-19
申请号：US16563104
申请日：2019-09-06
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Anuwat Saetow , David D. Cadigan , William V. Huott , Adam J. McPadden
Abstract: A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.
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公开(公告)号：US10606696B2
公开(公告)日：2020-03-31
申请号：US15830054
申请日：2017-12-04
Applicant: International Business Machines Corporation
Inventor： David D. Cadigan , Stephen Glancy , Frank LaPietra , Kevin McIlvain , Jeremy R. Neaton , Richard D. Wheeler
Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.
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公开(公告)号：US20190171520A1
公开(公告)日：2019-06-06
申请号：US15830054
申请日：2017-12-04
Applicant: International Business Machines Corporation
Inventor： David D. Cadigan , Stephen Glancy , Frank LaPietra , Kevin McIlvain , Jeremy R. Neaton , Richard D. Wheeler
Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.
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