公开(公告)号：US20180269144A1

公开(公告)日：2018-09-20

申请号：US15983672

申请日：2018-05-18

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/49872 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

公开(公告)号：US10049974B2

公开(公告)日：2018-08-14

申请号：US15251450

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee

IPC: H01L21/44 ,  H01L23/498 ,  H01L21/48

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

公开(公告)号：US20180114750A1

公开(公告)日：2018-04-26

申请号：US15816414

申请日：2017-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Joe Lee ,  Christopher J. Penny

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.

公开(公告)号：US09786760B1

公开(公告)日：2017-10-10

申请号：US15280457

申请日：2016-09-29

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L29/49 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US20190157146A1

公开(公告)日：2019-05-23

申请号：US16250561

申请日：2019-01-17

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Takeshi Nogami ,  Christopher J. Penny

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/321

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

公开(公告)号：US10177076B2

公开(公告)日：2019-01-08

申请号：US15683322

申请日：2017-08-22

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L23/482 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US09793193B1

公开(公告)日：2017-10-17

申请号：US15299906

申请日：2016-10-21

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L23/482 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US10211138B2

公开(公告)日：2019-02-19

申请号：US15983672

申请日：2018-05-18

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/532 ,  H01L23/528

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

公开(公告)号：US20180108596A1

公开(公告)日：2018-04-19

申请号：US15835749

申请日：2017-12-08

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L23/482 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/485 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US20180090418A1

公开(公告)日：2018-03-29

申请号：US15683324

申请日：2017-08-22

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC: H01L23/482 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.