-
公开(公告)号：US10573606B2
公开(公告)日：2020-02-25
申请号：US16271062
申请日：2019-02-08
发明人： Kafai Lai , Rasit O Topaloglu
IPC分类号： G06F17/50 , H03K19/195 , B65D33/28 , B65D33/16 , H01L23/00 , H01L23/544 , H01L21/67 , G06F19/00
摘要： Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.
-
公开(公告)号：US10381463B2
公开(公告)日：2019-08-13
申请号：US15875619
申请日：2018-01-19
IPC分类号： H01L21/308 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/033
摘要： Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
-
公开(公告)号：US10312200B2
公开(公告)日：2019-06-04
申请号：US15662258
申请日：2017-07-27
发明人： Kafai Lai , Rasit O Topaloglu
IPC分类号： H01L23/00 , H01L21/00 , G06F17/50 , G06F19/00 , H03K19/195 , B65D33/28 , H01L23/544 , H01L21/67 , B65D33/16
摘要： A semiconductor product includes a substrate having a self-assembly (SA) pattern. An initial SA pattern is created using a block copolymer (BCP) which has been annealed on the substrate. The initial SA pattern and/or an enlarged SA pattern derived from the initial SA pattern is incorporated into the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product. In other embodiments of the invention a method and system for creating the semiconductor product are described.
-
公开(公告)号：US20190080958A1
公开(公告)日：2019-03-14
申请号：US15703097
申请日：2017-09-13
发明人： Cheng Chi , Kafai Lai , Chi-Chun Liu , Yongan Xu
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L21/76816 , H01L21/02118 , H01L21/02356 , H01L21/31133 , H01L21/31138 , H01L21/76897
摘要： A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.
-
公开(公告)号：US20180012795A1
公开(公告)日：2018-01-11
申请号：US15206789
申请日：2016-07-11
发明人： Hsueh-Chung Chen , Cheng Chi , Lin Hu , Kafai Lai , Chi-Chun Liu , Jed W. Pitera
IPC分类号： H01L21/768 , H01L21/02 , G06F17/50 , H01L23/528 , H01L23/522
CPC分类号： H01L21/76816 , G06F17/5072 , H01L21/02118 , H01L21/02318 , H01L23/5226 , H01L23/528
摘要： A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.
-
公开(公告)号：US09581899B2
公开(公告)日：2017-02-28
申请号：US13686058
申请日：2012-11-27
发明人： Michael A. Guillorn , Kafai Lai , Jed W. Pitera , Hsinyu Tsai
IPC分类号： G03F7/40 , G03F7/00 , H01L21/033 , H01L21/311 , B81C1/00 , H01L21/768 , B81B7/00 , G03F7/16
CPC分类号： G03F7/0002 , B81B7/0006 , B81B2203/0353 , B81B2207/07 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , G03F7/0035 , G03F7/165 , H01L21/0337 , H01L21/3086 , H01L21/31144
摘要： After formation of a template layer over a neutral polymer layer, a self-assembling block copolymer material is applied and self-assembled. The template layer includes a first linear portion, a second linear portion that is shorter than the first linear portion, and blocking template structures having a greater width than the second linear portion. The self-assembling block copolymer material is phase-separated into alternating lamellae in regions away from the widthwise-extending portion. The blocking template structures perturb, and cause termination of, the lamellae. A cavity parallel to the first and second linear portions and terminating in self-alignment to the blocking template structures is formed upon selective removal of a polymeric block component. The pattern of the cavity can be inverted and transferred into the material layer to form fins having different lengths.
摘要翻译： 在中性聚合物层上形成模板层之后，自组装嵌段共聚物材料被应用并自组装。 模板层包括第一直线部分，比第一直线部分短的第二直线部分，以及阻挡具有比第二直线部分更大的宽度的模板结构。 自组装嵌段共聚物材料在远离宽度方向延伸部分的区域中相分离成交替的薄片。 阻挡模板结构扰乱并导致薄片的终止。 在选择性去除聚合物嵌段组分时，形成平行于第一和第二直线部分并终止于与阻挡模板结构自对准的空腔。 空腔的图案可以反转并转移到材料层中以形成具有不同长度的翅片。
-
17.发明申请公开(公告)号：US20160350466A1
公开(公告)日：2016-12-01
申请号：US14750742
申请日：2015-06-25
发明人： Michael A. Guillorn , Kafai Lai , Melih Ozlem , Hsinyu Tsai
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F7/0002 , G06F17/5068 , G06F2217/12 , H01L27/0886 , Y02P90/265
摘要： A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.
-
公开(公告)号：US11593470B2
公开(公告)日：2023-02-28
申请号：US16453945
申请日：2019-06-26
发明人： Rasit O Topaloglu , Kafai Lai
IPC分类号： G06F21/36 , G06F9/451 , G06F3/0481 , G06T13/20 , G06F3/04815
摘要： A method, apparatus and computer program product for using a volumetric CAPTCHA display to verify that a human is present at a computer. Responsive to a request for a computer resource, a volumetric CAPTCHA is displayed in a user interface at the computer. The volumetric CAPTCHA has a first three dimensional (3D) feature and a second 3D feature. The user is prompted to answer a question about the first 3D feature of the volumetric CAPTCHA display. The received user response to the question is evaluated for correctness in describing the first 3D feature of the volumetric CAPTCHA. In response to the received user response being correct, the user is allowed access to the computer resource. The first 3D feature and the second 3D feature have a relationship with each other in the volumetric CAPTCHA.
-
公开(公告)号：US20220181154A1
公开(公告)日：2022-06-09
申请号：US17677469
申请日：2022-02-22
发明人： Rasit Onur Topaloglu , Kafai Lai , Dongbing Shao , Zheng Xu
IPC分类号： H01L21/033 , H01L23/528 , H01L21/768 , H01L21/311
摘要： A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
-
公开(公告)号：US11314108B2
公开(公告)日：2022-04-26
申请号：US16541860
申请日：2019-08-15
摘要： An apparatus includes two or more tunable antennas providing a reconfigurable metasurface, each of the tunable antennas including a plurality of pixels of optically tunable material, and a control circuit including switches providing current sources and a ground voltage, the switches being coupled to respective ones of the pixels of optically tunable material in each of the tunable antennas via first electrodes, the ground voltage being coupled to respective ones of the pixels of optically tunable material in each of the tunable antennas via second electrodes. The control circuit is configured to modify states of respective ones of the plurality of pixels of optically tunable material in the tunable antennas utilizing current supplied between the first electrodes and the second electrodes to adjust reflectivity of the plurality of pixels of optically tunable material in each of the tunable antennas to dynamically reconfigure respective antenna shape configurations of the tunable antennas.
-
-
-
-
-
-
-
-
-
搜索结果
63 条记录 (耗时 0.024 秒)
