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公开(公告)号:US11823724B2
公开(公告)日:2023-11-21
申请号:US17510436
申请日:2021-10-26
Applicant: International Business Machines Corporation
Inventor: Saba Zare , Dimitri Houssameddine , Karthik Yogendra , Heng Wu
CPC classification number: G11C11/161 , G11C11/1655 , G11C11/1673 , G11C11/1697 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer; and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.
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公开(公告)号:US11514962B2
公开(公告)日:2022-11-29
申请号:US17096064
申请日:2020-11-12
Applicant: International Business Machines Corporation
Inventor: Karthik Yogendra , Eric Raymond Evarts
Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.
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公开(公告)号:US11335850B2
公开(公告)日:2022-05-17
申请号:US16816322
申请日:2020-03-12
Applicant: International Business Machines Corporation
Inventor: Karthik Yogendra , Robert Robison , Eric Raymond Evarts
Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.
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公开(公告)号:US20210288242A1
公开(公告)日:2021-09-16
申请号:US16816322
申请日:2020-03-12
Applicant: International Business Machines Corporation
Inventor: Karthik Yogendra , Robert ROBISON , Eric Raymond Evarts
Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.
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公开(公告)号:US20230411533A1
公开(公告)日:2023-12-21
申请号:US17806952
申请日:2022-06-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Karthik Yogendra , Maruf Amin Bhuiyan , Kangguo Cheng
IPC: H01L29/792 , H01L29/78
CPC classification number: H01L29/792 , H01L29/7846 , H01L29/785
Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a composite channel of multiple channel layers of different materials, wherein the multiple channel layers are separated from each other by an isolation layer and a material of the isolation layer has a bandgap that is wider than bandgaps of the different materials of the multiple channel layers; a charge trapping layer surrounding the composite channel; a gate metal surrounding the charge trapping layer; and source/drain regions at a first and a second end of the composite channel. A method of forming the same is also provided.
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公开(公告)号:US11664059B2
公开(公告)日:2023-05-30
申请号:US17336994
申请日:2021-06-02
Applicant: International Business Machines Corporation
Inventor: Dimitri Houssameddine , Saba Zare , Heng Wu , Karthik Yogendra
CPC classification number: G11C11/161 , G11C11/1673 , G11C11/1675 , G11C27/005 , H01F10/3254 , H01F10/3286 , H10N50/01 , H10N50/80
Abstract: A memory system may include a magnetic tunnel junction stack, a first high resistance tunnel barrier, and a first voltage controlled magnetic anisotropy write layer. The first voltage controlled magnetic anisotropy write layer may be adjacent the high resistance tunnel barrier, and the voltage controlled magnetic anisotropy write line may include a magnetic material in direct contact with a high resistance tunnel barrier.
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公开(公告)号:US20230074676A1
公开(公告)日:2023-03-09
申请号:US17469350
申请日:2021-09-08
Applicant: International Business Machines Corporation
Inventor: Julien Frougier , Karthik Yogendra , Dimitri Houssameddine , Kangguo Cheng , Ruilong Xie
Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode u can be made a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.
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公开(公告)号:US20220148635A1
公开(公告)日:2022-05-12
申请号:US17096064
申请日:2020-11-12
Applicant: International Business Machines Corporation
Inventor: Karthik Yogendra , Eric Raymond Evarts
Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.
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公开(公告)号:US10978573B2
公开(公告)日:2021-04-13
申请号:US16504739
申请日:2019-07-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Karthik Yogendra , Ardasheir Rahman , Robert Robison , Adra Carr
IPC: H01L29/66 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L27/092 , H01L29/78 , H01L29/08
Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.
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公开(公告)号:US10833258B1
公开(公告)日:2020-11-10
申请号:US16402126
申请日:2019-05-02
Applicant: International Business Machines Corporation
Inventor: Ashim Dutta , Chih-Chao Yang , Daniel C. Edelstein , Karthik Yogendra , John C. Arnold
Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
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