公开(公告)号：US20240203780A1

公开(公告)日：2024-06-20

申请号：US18083380

申请日：2022-12-16

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Ruilong Xie ,  Stuart Sieg ,  Fee Li Lie ,  Kisik Choi

IPC: H01L21/683 ,  H01L23/544

CPC classification number: H01L21/6835 ,  H01L23/544 ,  H01L2221/68309 ,  H01L2221/68327 ,  H01L2223/54426

Abstract: A semiconductor structure includes a handler substrate and a device substrate bonded to the handler substrate. The handler substrate comprises a trench, and at least one alignment mark in a bottom surface of the trench. One or more dielectric layers are disposed in the trench and on the at least one alignment mark.

公开(公告)号：US20230317802A1

公开(公告)日：2023-10-05

申请号：US17657006

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Junli Wang ,  Brent A Anderson ,  Terence Hook ,  Indira Seshadri ,  Albert M. Young ,  Stuart Sieg ,  Su Chen Fan ,  Shogo Mochizuki

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41725 ,  H01L29/401

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

公开(公告)号：US20230154783A1

公开(公告)日：2023-05-18

申请号：US17527229

申请日：2021-11-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Kevin Shawn Petrarca

IPC: H01L21/74 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/743 ,  H01L21/76879 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/5286 ,  H01L27/0886

Abstract: Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (BPR) under the device region. A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D. The semiconductor structure may also include a via-contact-to-buried power rail (VBPR) between the BPR and the S/D.

公开(公告)号：US20230143705A1

公开(公告)日：2023-05-11

申请号：US17522015

申请日：2021-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Indira Seshadri ,  Stuart Sieg ,  Su Chen Fan

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66742

Abstract: A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

公开(公告)号：US20230100113A1

公开(公告)日：2023-03-30

申请号：US17488389

申请日：2021-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Rishikesh Krishnan ,  Alexander Reznicek

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

公开(公告)号：US12080559B2

公开(公告)日：2024-09-03

申请号：US17546443

申请日：2021-12-09

Applicant: International Business Machines Corporation

Inventor： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/66545

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

公开(公告)号：US20240203984A1

公开(公告)日：2024-06-20

申请号：US18067968

申请日：2022-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Indira Seshadri ,  Jay William Strane ,  Stuart Sieg

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Semiconductor devices and methods of forming the same include a lower semiconductor device over a substrate, the lower semiconductor device having a first width. An upper semiconductor device is over the lower semiconductor device. The upper semiconductor device has a second width smaller than the first width. A dielectric structure is over the lower semiconductor device and has a first sidewall that faces the upper semiconductor device and a second sidewall that aligns vertically with a sidewall of the lower semiconductor device.

公开(公告)号：US11990412B2

公开(公告)日：2024-05-21

申请号：US17488389

申请日：2021-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Rishikesh Krishnan ,  Alexander Reznicek

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

公开(公告)号：US20230420503A1

公开(公告)日：2023-12-28

申请号：US17808566

申请日：2022-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Stuart Sieg ,  Xuan Liu ,  Junli Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851

Abstract: A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

公开(公告)号：US20230411212A1

公开(公告)日：2023-12-21

申请号：US17807006

申请日：2022-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Stuart Sieg ,  Dominik Metzler ,  Indira Seshadri ,  Junli Wang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H01L21/76877

Abstract: A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.