公开(公告)号：US10027349B2

公开(公告)日：2018-07-17

申请号：US14835804

申请日：2015-08-26

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Adam J. McPadden

IPC: G06F11/10 ,  G11C29/00 ,  H03M13/00

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

公开(公告)号：US09880896B2

公开(公告)日：2018-01-30

申请号：US14320283

申请日：2014-06-30

Applicant: International Business Machines Corporation

Inventor： Paul W. Coteus ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Vipinchandra Patel

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/073 ,  G06F11/1048

Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

公开(公告)号：US09747148B2

公开(公告)日：2017-08-29

申请号：US15401744

申请日：2017-01-09

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1024 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/19

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

公开(公告)号：US09734095B2

公开(公告)日：2017-08-15

申请号：US14841787

申请日：2015-09-01

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Stephen P. Glancy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/0246 ,  G06F21/88 ,  G06F2212/1052 ,  G06F2212/7209

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.

公开(公告)号：US20170154660A1

公开(公告)日：2017-06-01

申请号：US15406655

申请日：2017-01-13

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, JR. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C7/22 ,  G11C29/50 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/50012 ,  G11C2029/5004 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

公开(公告)号：US09620184B1

公开(公告)日：2017-04-11

申请号：US14970798

申请日：2015-12-16

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, Jr. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C5/14 ,  G11C7/22 ,  G11C29/02

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

公开(公告)号：US09606851B2

公开(公告)日：2017-03-28

申请号：US14611351

申请日：2015-02-02

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1024 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/19

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

公开(公告)号：US09471423B1

公开(公告)日：2016-10-18

申请号：US14974393

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.

Abstract translation: 可以在存储器设备内的第一地址处识别可校正的存储器错误。 基于至少所述识别，可以将第一可校正存储器错误计数从第一数量更新为第二数量。 可以确定第二数量超过或不超过阈值。 响应于确定，第二数量的第一可校正存储器错误计数可以：转换为第三数量并相应地报告给主机设备，报告给主机设备，或者不向主机设备报告。

公开(公告)号：US20160239663A1

公开(公告)日：2016-08-18

申请号：US14621506

申请日：2015-02-13

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F21/55 ,  G06F11/07

CPC classification number: G06F21/554 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F2221/034 ,  G11C7/24 ,  G11C11/40 ,  G11C2029/0411

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract translation: 本公开的实施例提供了一种用于监视动态随机存取存储器（DRAM）设备以检测和响应低温攻击的方法，计算机程序产品和系统。 处理器接收关于DRAM设备的一组存储器信息。 然后处理器通过使用一组决策参数处理存储器信息来确定一组错误指示符。 然后将错误指示符与攻击综合征进行比较，以确定DRAM是否正在经历低温攻击。 如果DRAM正在经历低温攻击，则禁用对DRAM器件的访问。

公开(公告)号：US09251894B2

公开(公告)日：2016-02-02

申请号：US14466335

申请日：2014-08-22

Applicant: International Business Machines Corporation

Inventor： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G11C5/06 ,  G11C13/00 ,  G11C5/02 ,  G11C7/00 ,  G11C7/12

CPC classification number: G11C13/0026 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79

Abstract: Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.