公开(公告)号：US20190165109A1

公开(公告)日：2019-05-30

申请号：US16247989

申请日：2019-01-15

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar ,  Yu Zhu

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/205 ,  H01L21/02241 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

公开(公告)号：US10167443B2

公开(公告)日：2019-01-01

申请号：US15334863

申请日：2016-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Mahmoud Khojasteh ,  Masahiro Nakamura ,  Satyavolu S. Papa Rao ,  Bang N. To ,  George G. Totir ,  Yu Zhu

IPC: C11D3/04 ,  C11D7/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  C11D11/00 ,  H01L29/66 ,  H01L21/3065

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

公开(公告)号：US10043711B2

公开(公告)日：2018-08-07

申请号：US15490414

申请日：2017-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Kevin K. Chan ,  John Rozen ,  Jeng-Bang Yau ,  Yu Zhu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/18 ,  H01L21/3215 ,  H01L21/02

Abstract: A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.

公开(公告)号：US09865688B2

公开(公告)日：2018-01-09

申请号：US14213511

申请日：2014-03-14

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar ,  Yu Zhu

IPC: H01L29/205 ,  H01L23/522 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/205 ,  H01L21/02241 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A structure and method for forming a substrate, a buffer layer disposed on the substrate, an oxide layer disposed on the buffer layer, and a fin comprising a semiconductor material disposed on the oxide layer.

公开(公告)号：US09536731B2

公开(公告)日：2017-01-03

申请号：US14523515

申请日：2014-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Mahmoud Khojasteh ,  Masahiro Nakamura ,  Satyavolu S. Papa Rao ,  Bang N. To ,  George G. Totir ,  Yu Zhu

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  C11D11/00 ,  C11D7/10

CPC classification number: C11D7/105 ,  C11D11/0047 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/28008 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/66575

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract translation: 一种用于清洗蚀刻残留物的方法，其可以包括用含水镧系溶液处理蚀刻表面，其中所述含水镧系溶液除去包括大部分烃和至少一种选自碳，氧，氟的元素的蚀刻残渣 ，氮和硅。 在一个实例中，水溶液可以是硝酸铈铵（Ce（NH 4）（NO 3）），（CAN）。

公开(公告)号：US09159834B2

公开(公告)日：2015-10-13

申请号：US13828867

申请日：2013-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Zhen Zhang ,  Yu Zhu

IPC: H01L29/78 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/04 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/7853 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics.

Abstract translation: 在半导体鳍片上进行半导体材料的选择性外延以形成半导体纳米线。 半导体纳米线的表面包括非水平和非垂直的面。 可以在半导体纳米线上形成栅电极，使得刻面可以用作沟道表面。 小面半导体纳米线的外延沉积部分可以对通道施加应力。 此外，在形成栅电极之前，可以添加附加的半导体材料以形成刻面半导体纳米线的外壳。 半导体纳米线的刻面提供明确定义的电荷载流子传输性质，其可以有利地用于提供具有良好控制的器件特性的半导体器件。

公开(公告)号：US10825514B2

公开(公告)日：2020-11-03

申请号：US15958833

申请日：2018-04-20

Applicant: International Business Machines Corporation

Inventor： Wanki Kim ,  Matthew Joseph BrightSky ,  Yu Zhu ,  Yujun Xie

IPC: G11C13/00 ,  H01L45/00 ,  G11C11/56

Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.

公开(公告)号：US10692574B2

公开(公告)日：2020-06-23

申请号：US16290353

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Wanki Kim ,  Chung Hon Lam ,  Yu Zhu ,  Yujun Xie

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L21/66

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.

公开(公告)号：US20190325954A1

公开(公告)日：2019-10-24

申请号：US15958833

申请日：2018-04-20

Applicant: International Business Machines Corporation

Inventor： Wanki Kim ,  Matthew Joseph BrightSky ,  Yu Zhu ,  Yujun Xie

IPC: G11C13/00 ,  G11C11/56 ,  H01L45/00

Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.

公开(公告)号：US10319440B1

公开(公告)日：2019-06-11

申请号：US15937176

申请日：2018-03-27

Applicant: International Business Machines Corporation

Inventor： Wanki Kim ,  Chung Hon Lam ,  Yu Zhu ,  Yujun Xie

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L21/66

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.