公开(公告)号：US09653579B2

公开(公告)日：2017-05-16

申请号：US14281021

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

公开(公告)号：US09646962B1

公开(公告)日：2017-05-09

申请号：US15285985

申请日：2016-10-05

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/861 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0255 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66121 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/7391 ,  H01L29/87

Abstract: A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a substrate, the first finFET and the ESD device. The first finFET is formed such that it includes finFET fins extending from the substrate. The ESD device includes two vertically stacked PN diodes including vertically stacked first, second, third and fourth layers. The first layer is an N doped layer and is disposed directly over the substrate, the second layer is a P doped layer and is disposed directly over the first layer, the third layer is an N doped layer and is disposed directly over the second layer and the fourth layer is a P doped layer and is disposed directly over the third layer.

公开(公告)号：US20170033197A1

公开(公告)日：2017-02-02

申请号：US15181843

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L21/306 ,  H01L29/08

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract translation: 半导体器件包括在衬底中图案化的鳍; 设置在所述翅片上并基本上垂直于所述翅片的门; 一对外延触点，包括在鳍的上方和栅极的相对侧上的III-V材料; 以及在栅极之间的一对外延触点之间的沟道区，其包括在掺杂III-V材料之间的未掺杂的III-V材料，掺杂的III-V材料包括量为约1e18至约1e20原子/ 并与外延触点接触。

公开(公告)号：US09502292B2

公开(公告)日：2016-11-22

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/20 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US20160284822A1

公开(公告)日：2016-09-29

申请号：US15178853

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20160284599A1

公开(公告)日：2016-09-29

申请号：US15179620

申请日：2016-06-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/84

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US09412820B2

公开(公告)日：2016-08-09

申请号：US14456272

申请日：2014-08-11

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Tenko Yamashita ,  Chun-chen Yeh ,  Veeraraghavan S. Basker

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/1037 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Abstract translation: 制造半导体器件的方法可以包括在绝缘层上形成半导体层之上的虚拟栅极，在半导体层上方形成侧壁间隔，在虚设栅极的相对侧上，在侧壁间隔物的相对侧上形成源极和漏极区域 并且在侧壁间隔物之间​​移除半导体层的虚拟栅极和下面的部分，以提供厚度小于稀薄沟道区域外的半导体层的剩余部分的薄化沟道区域。 该方法还可以包括在稀疏的沟道区域和侧壁间隔物之间​​形成替代栅极堆叠，并且具有在侧壁间隔物的相邻底部的水平面下方延伸的下部。

公开(公告)号：US09299721B2

公开(公告)日：2016-03-29

申请号：US14280998

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L21/30 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。

公开(公告)号：US20150372107A1

公开(公告)日：2015-12-24

申请号：US14308014

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract translation: 描述了与形成翅片间距小于30nm的finFET相关联的方法和结构。 可以在栅极上的间隔物形成期间使用选择性氮化工艺，以使得能够使用传统间隔物沉积工艺可以获得更细的翅片间距。 间隔物形成还可以允许对源极和漏极结的形成的精确控制。

公开(公告)号：US20150364578A1

公开(公告)日：2015-12-17

申请号：US14307011

申请日：2014-06-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L29/20 ,  H01L29/205 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract translation: 描述了形成finFET的电阻减小区域的方法和结构。 根据一些方面，可以在包括第一半导体组合物的鳍片之上形成伪栅极和第一栅极间隔物。 可以去除鳍的源区和漏区的至少一部分，并且可以在与第一半导体组合物接触的源区和漏区中形成第二半导体组合物。 可以形成覆盖第一栅极间隔物的第二栅极间隔物。 该方法可用于形成在源极和漏极结处具有降低的电阻的finFET。