公开(公告)号：US20220181211A1

公开(公告)日：2022-06-09

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US20190088550A1

公开(公告)日：2019-03-21

申请号：US16081236

申请日：2017-02-27

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/56 ,  H01L23/48 ,  H01L25/065

Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

公开(公告)号：US20180138120A1

公开(公告)日：2018-05-17

申请号：US15804396

申请日：2017-11-06

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/528 ,  H01L21/32139 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/482 ,  H01L23/49527 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/53238 ,  H01L23/535 ,  H01L23/562 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7813 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

公开(公告)号：US20170271446A1

公开(公告)日：2017-09-21

申请号：US15457833

申请日：2017-03-13

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Oliver Blank ,  Oliver Hellmund ,  Martin Poelzl

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/78 ,  H01L29/78 ,  B81B7/00 ,  B81C1/00 ,  H01L29/40 ,  H01L29/10 ,  H01L21/683

CPC classification number: H01L29/0696 ,  B81B3/0072 ,  B81B7/008 ,  B81B2207/015 ,  B81C1/00246 ,  B81C2203/0707 ,  G01C19/5733 ,  G01P15/125 ,  H01L21/6835 ,  H01L21/78 ,  H01L29/02 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2221/68327

Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

公开(公告)号：US20150041816A1

公开(公告)日：2015-02-12

申请号：US14447896

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 本公开涉及一种半导体器件，其包括在从第一表面延伸到半导体本体的第一沟槽中具有IGFET的第一表面，第一表面，包括多晶硅的栅电极结构的半导体本体。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。

公开(公告)号：US11848237B2

公开(公告)日：2023-12-19

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/8234 ,  H01L21/561 ,  H01L21/762 ,  H01L21/76873 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49562 ,  H01L25/0655 ,  H01L23/3114 ,  H01L23/3135 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US10672664B2

公开(公告)日：2020-06-02

申请号：US16081236

申请日：2017-02-27

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/78 ,  H01L21/8234 ,  H01L21/56 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

公开(公告)号：US09917160B2

公开(公告)日：2018-03-13

申请号：US15098789

申请日：2016-04-14

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L29/04 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/8605 ,  H01L29/861 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

公开(公告)号：US20160190256A1

公开(公告)日：2016-06-30

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 半导体器件包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。

公开(公告)号：US20140106555A1

公开(公告)日：2014-04-17

申请号：US14132008

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Martin Poelzl

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/28035 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7813

Abstract: A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.

Abstract translation: 一种形成半导体器件的方法。 一个实施例提供了具有侧壁隔离的沟槽的半导体衬底。 在沟槽的一部分中去除侧壁隔离。 栅极电介质形成在铺设的敞开的侧壁上。 与日期电介质相邻地形成栅电极。 栅电极的上表面位于半导体衬底的表面下方的深度d1处。 在栅电极上方去除栅极氧化物。 在栅电极和半导体衬底上同时形成隔离，使得栅电极之间的隔离和半导体衬底之间的隔离之间的高度差d2的绝对值小于深度d1。